Interlayer Buffer Structure for Thicker HEMT Epitaxial Stacks

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Solution Overview

Problem

High electron mobility transistors (HEMTs) face issues with tensile stress-induced defects and limited thickness due to lattice mismatch and thermal expansion mismatch, leading to cracking and dislocations, which restrict their performance and reliability.

Innovation Solution

Incorporating interlayer buffer layers formed at a lower temperature between superlattice layers to reduce tensile stress, allowing for increased epitaxial stack thickness and improved crystal quality, thereby enhancing the performance and reliability of HEMTs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the epitaxial stack thickness is increased to improve high voltage device performance, then the device performance and reliability are improved, but tensile stress-induced cracking and dislocations occur due to lattice mismatch and thermal expansion mismatch

Engineering Contradiction:
Improvedevice reliabilityVSAvoidstructural integrity
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The buffer structure is segmented into multiple functional layers: a first buffer layer, a superlattice layer with alternating high and low band gap semiconductor layers, and a second buffer layer. This segmentation allows each layer to address specific stress and defect issues, enabling thicker epitaxial stacks without cracking while maintaining structural integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The superlattice layer employs composite materials with alternating high band gap and low band gap semiconductor layers. This composite structure creates a gradient that manages lattice mismatch and thermal expansion differences, reducing tensile stress in thicker devices while maintaining crystal quality.

Inventive Principle:
Principle #40Composite materials

2Power

If the epitaxial stack thickness is increased to improve device performance, then the breakdown voltage and power handling are improved, but tensile stress causes cracking and dislocations

Engineering Contradiction:
Improvepower handlingVSAvoidtensile stress-induced defects
Core Design Contradiction:
PowerVSObject-affected harmful factors

Solution Approach 1:

The buffer structure with superlattice layers is prepared in advance before forming the active device layers. This preliminary structure pre-manages the tensile stress that would otherwise develop in thicker epitaxial stacks, preventing cracking and dislocations before they occur during device operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The superlattice layer changes the band gap parameter gradually through alternating high and low band gap semiconductor layers. This parameter gradient allows the structure to accommodate thicker epitaxial stacks by managing stress distribution, enabling improved power handling without tensile stress-induced defects.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If conventional buffer structures are used, then the device can be manufactured with standard processes, but the crystal quality deteriorates and defects increase in thicker devices

Engineering Contradiction:
Improvecrystal qualityVSAvoidbuffer structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The buffer structure is divided into distinct segments: a first buffer layer, a superlattice layer with multiple alternating semiconductor layers, and a second buffer layer. This segmentation allows standard manufacturing processes to be applied to each layer while achieving superior crystal quality in thicker devices through the cumulative effect of the structured buffer.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The interlayer buffer layers mitigate tensile stress, reducing cracking and dislocations, enabling thicker epitaxial stacks and improved performance and reliability of high voltage devices.

Implementation Method 1

the interlayer buffer layers formed at a lower temperature than the superlattice layers and configured to reduce tensile stress in the superlattice layers and the channel layer

Methodology Applied
Scientific EffectStress relief: Stress Relaxation

Data Source

PatentUS20240266403A1Buffer structure with interlayer buffer layers for high voltage device
Publication Date: 2024.08.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240266403A1 patent drawing
  • US20240266403A1 patent drawing
  • US20240266403A1 patent drawing

AI summary

Various embodiments of the present disclosure are directed towards an integrated chip a semiconductor device including a plurality of superlattice layers disposed over a substrate. The plurality of superlattice layers include a first superlattice layer overlying a second superlattice layer. A channel layer overlies the plurality of superlattice layers. An active layer overlies the channel layer. A first interlayer buffer layer is disposed directly between the first superlattice layer and the second superlattice layer. The first interlayer buffer layer comprises a first density of dislocations greater than a second density of dislocations in the first superlattice layer.