Interlayer Capacitor and Resistor Layout for Dense Wiring Stacks
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Solution Overview
Problem
In semiconductor devices with increasing numbers of wiring layers, the placement of capacitor elements and resistor elements between layers poses challenges. The relative accuracy of capacitor elements is affected by wiring configurations, and the characteristics of resistor elements can vary due to over-etching risks, especially with shorter distances between wiring layers.
Innovation Solution
A semiconductor device design that includes a first wiring layer with a thinner first wiring, a second wiring layer with thicker second and third wirings, and dielectric and conductive films forming a capacitor element between these layers. The resistor element is formed between the uppermost wiring layer and a lower wiring layer, with specific thicknesses and interlayer dielectric films to mitigate over-etching risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conductor is used as the lower electrode of a capacitor element, then the capacitor element can be formed in the wiring layer, but the relative accuracy changes depending on the wiring configuration
Solution Approach 1:
A dedicated lower electrode layer is introduced as an intermediary between the wiring layer and the capacitor dielectric film. This separate lower electrode layer is not used for signal routing but specifically for forming capacitor elements, thereby isolating the capacitor characteristics from wiring configuration variations and improving relative accuracy.
2Volume of moving object
If the thickness of the upper wiring is large and the thickness of the interlayer dielectric film is small, then the device can be miniaturized, but the over-etching may reach the resistor element during patterning
Solution Approach 1:
The thickness of the interlayer dielectric film covering the resistor element is designed to be greater than the over-etching amount, creating a protective cushion that prevents the etching process from reaching the resistor element during upper wiring patterning, thereby maintaining resistor characteristics while allowing device miniaturization.
3Length of moving object
If the distance between wiring layers is shortened, then the device can be miniaturized, but the risk of over-etching reaching the resistor element increases
Solution Approach 1:
The interlayer dielectric film is designed with different thicknesses in different regions: a greater thickness in the region covering the resistor element to prevent over-etching, and a smaller thickness in other regions to enable device miniaturization. This local variation in quality allows simultaneous achievement of miniaturization and manufacturing precision.
Data Source
AI summary
A lower electrode is formed in a first wiring layer. In a second wiring layer located over the first wiring layer, two wirings having a thickness greater than that of the lower electrode are formed. Between the first wiring layer and the second wiring layer, a dielectric film and an upper electrode are formed over the lower electrode. A resistor element is formed over the two wirings. The lower electrode, the dielectric film, and the upper electrode function as a capacitor element.