Interlayer Semiconductor Chip Warpage Suppression
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Solution Overview
Problem
In semiconductor devices with stacked chip configurations, the warpage of semiconductor chips during wire bonding due to lack of support from underlying chips leads to defective bonding, particularly in staircase configurations where chip thickness uniformity is desired to prevent footprint increase and facilitate thinning.
Innovation Solution
Incorporating interlayer semiconductor chips with thicker protruding portions that do not overlap or underlap adjacent chip groups, enhancing the rigidity of these portions to prevent warpage while maintaining uniform thickness in the stacked configuration, thus improving wire bonding yield without hindering device thinning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If uniform thickness is used for all chips in the stacked configuration, then the footprint is prevented from increasing and device thinning is facilitated, but warpage occurs during wire bonding due to lack of support from underlying chips
Solution Approach 1:
The patent applies local quality by making the lowermost chip of the second element group thicker than other chips. This localized thickness variation provides support to the lowermost chip during wire bonding, preventing warpage and defective bonding, while maintaining uniform thickness for all other chips to avoid footprint increase and facilitate device thinning.
2Reliability
If the lowermost chip of the second element group is made thicker, then warpage is suppressed and wire bonding yield is improved, but the overall device thickness increases
Solution Approach 1:
The patent applies local quality by making the lowermost chip of the second element group thicker than other chips. This localized thickness variation provides support to the lowermost chip during wire bonding, preventing warpage and defective bonding, while maintaining uniform thickness for all other chips to avoid footprint increase and facilitate device thinning.
3Area of stationary object
If staircase configuration is used for stacked chips, then footprint increase is prevented, but support from underlying chips is reduced causing warpage during wire bonding
Solution Approach 1:
The patent applies local quality by making the lowermost chip of the second element group thicker than other chips. This localized thickness variation provides support to the lowermost chip during wire bonding, preventing warpage and defective bonding, while maintaining uniform thickness for all other chips to avoid footprint increase and facilitate device thinning.
Data Source
AI summary
According to one embodiment, the first end part of the first semiconductor chip in a lower stage protrudes to a larger extent in a first direction than the first end part of the first semiconductor chip in an upper stage. The second end part of the second semiconductor chip in a lower stage protrudes to a larger extent in a second direction opposite from the first direction than the second end part of the second semiconductor chip in an upper stage. The first interlayer semiconductor chip includes a first portion, a second portion, and a third electrode pad. The first portion overlaps the first chip group. The second portion protrudes in the second direction beyond the first chip group and the second chip group and is thicker than the first portion. The third electrode pad is provided on the second portion and bonded with the third metal wire.