Interlayer Decoupling Capacitor Layout for Low-Leakage ICs
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Solution Overview
Problem
Existing decoupling capacitors in integrated circuits face challenges with high leakage current and density limitations, particularly when replacing I/O transistors with core transistors, leading to unsatisfactory performance and future integration issues.
Innovation Solution
The implementation of interlayer decoupling capacitors formed across different layers of a semiconductor device, where electrodes are positioned in various layers such as back-end-of-line, middle-end-of-line, and front-end-of-line layers, increasing density and reducing leakage current by vertically integrating conductive structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional decoupling capacitors are used in integrated circuits, then they can provide temporary charge reservoirs to prevent voltage fluctuations, but they suffer from high leakage current and density limitations
Solution Approach 1:
The patent transitions from planar decoupling capacitors to three-dimensional stacked capacitors, utilizing the vertical dimension to increase density. Multiple capacitor layers are stacked above each other, allowing multiple decoupling elements to occupy the same footprint area, thereby increasing the number of capacitors per unit area without increasing leakage current proportionally
2Quantity of substance
If I/O transistors are replaced with core transistors to increase density, then transistor density improves, but decoupling capacitor performance deteriorates due to high leakage current
Solution Approach 1:
By stacking capacitors vertically in multiple layers, the patent achieves high decoupling capacitor density that can accompany high transistor density, eliminating the need to compromise on capacitor performance when using core transistors
Solution Approach 2:
The patent embeds multiple decoupling capacitor layers within the vertical structure of the integrated circuit, nesting capacitors within the three-dimensional device architecture. This allows decoupling functionality to be integrated throughout the device volume rather than confined to a single plane
3Quantity of substance
If more decoupling capacitors are added to increase density, then capacitance density improves, but leakage current increases proportionally
Solution Approach 1:
The stacked capacitor architecture distributes leakage current across multiple vertically-separated layers rather than concentrating it in a single plane. This spatial distribution in the vertical dimension allows higher total capacitance density while the leakage current per unit area remains controlled
Data Source
AI summary
A semiconductor device includes an active region over a substrate extending along a first lateral direction. The semiconductor device includes a number of first conductive structures operatively coupled to the active region. The first conductive structures extend along a second lateral direction. The semiconductor device includes a number of second conductive structures disposed above the plurality of first conductive structures. The second conductive structures extend along the first lateral direction. The semiconductor device includes a first capacitor having a first electrode and a second electrode. The first electrode includes one of the first conductive structures and the active region, and the second electrode includes a first one of the second conductive structures. Each of the active region and the first conductive structures is electrically coupled to a power rail structure configured to carry a supply voltage.