Interlayer Decoupling Capacitors for High-Density Low-Leakage ICs

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Solution Overview

Problem

Existing decoupling capacitors in integrated circuits face challenges with high leakage current and density limitations, particularly when transitioning to next-generation technology nodes where intralayer decoupling capacitors in universal core areas encounter undesirable high leakage.

Innovation Solution

The implementation of interlayer decoupling capacitors, where electrodes are vertically integrated across different layers, such as from the back-end-of-line (BEOL) to the middle-end-of-line (MEOL) and front-end-of-line (FEOL) layers, increasing density and reducing leakage by tying one electrode to a power supply.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If intralayer decoupling capacitors are used in universal core areas, then device density is improved, but leakage current increases significantly

Engineering Contradiction:
Improvedevice densityVSAvoidleakage current
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent transitions from intralayer capacitors (single-layer configuration) to interlayer capacitors (multi-layer vertical configuration). By stacking capacitor electrodes across multiple layers (FEOL, MEOL, BEOL), the design exploits the vertical dimension to increase density while maintaining lower leakage characteristics through the distributed multi-layer architecture.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The capacitor structure is divided into multiple segments across different layers. Instead of a single large intralayer capacitor, the patent segments the capacitance function across multiple smaller electrode pairs distributed through FEOL, MEOL, and BEOL layers, reducing leakage while achieving equivalent or higher total capacitance density.

Inventive Principle:
Principle #1Segmentation

2Object-generated harmful factors

If interlayer decoupling capacitors are implemented, then leakage current is reduced, but device complexity increases

Engineering Contradiction:
Improveleakage currentVSAvoidstructure complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The interlayer capacitor structure serves multiple functions simultaneously: it provides decoupling capacitance, acts as part of the interconnect architecture, and utilizes existing layer structures from the manufacturing process. The same layered architecture that provides routing functionality also provides the capacitor electrodes, eliminating the need for separate dedicated capacitor structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The manufacturing process itself creates the capacitor structures as a byproduct of building the interconnect layers. The electrodes and dielectric layers required for capacitors are formed during the standard backend-of-line processing, so no additional dedicated capacitor fabrication steps are needed beyond normal interconnect formation.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly increases the density of decoupling capacitors by at least 1.3 to 1.7 times compared to intralayer capacitors while minimizing leakage current, effectively addressing the trade-off between density and leakage in existing technologies.

Implementation Method 1

decoupling capacitors are typically used, acting as temporary charge reservoirs to prevent momentary fluctuations in supply voltage

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11854960B2Semiconductor devices including decoupling capacitors and methods of manufacturing thereof
Publication Date: 2023.12.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11854960B2 patent drawing
  • US11854960B2 patent drawing
  • US11854960B2 patent drawing

AI summary

A semiconductor device includes an active region over a substrate extending along a first lateral direction. The semiconductor device includes a number of first conductive structures operatively coupled to the active region. The first conductive structures extend along a second lateral direction. The semiconductor device includes a number of second conductive structures disposed above the plurality of first conductive structures. The second conductive structures extend along the first lateral direction. The semiconductor device includes a first capacitor having a first electrode and a second electrode. The first electrode includes one of the first conductive structures and the active region, and the second electrode includes a first one of the second conductive structures. Each of the active region and the first conductive structures is electrically coupled to a power rail structure configured to carry a supply voltage.