Interlayer Dielectric Cusping Prevention in Semiconductor Fabrication
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Solution Overview
Problem
The integration density of semiconductor memory devices is limited by the formation of cusping in interlayer dielectrics, which can lead to reduced strength and reliability, and subsequent short-circuiting of contacts during the fabrication of semiconductor devices with stepwise structures.
Innovation Solution
A method involving the formation of a first interlayer dielectric with a low side step coverage using high-density plasma chemical vapor deposition and a second interlayer dielectric with higher side step coverage using plasma enhanced chemical vapor deposition, limiting cusping and enhancing the reliability and yield of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single interlayer dielectric is formed with high side step coverage to fully cover the stepped structure, then complete coverage is achieved, but cusping occurs reducing strength and reliability
Solution Approach 1:
The interlayer dielectric formation process is divided into two separate deposition steps: first forming an interlayer dielectric layer with low side step coverage (0-50%) to avoid cusping, then forming a planarization layer with high side step coverage (50-100%) to achieve complete coverage. This segmentation resolves the contradiction by assigning different functional requirements to different layers.
Solution Approach 2:
Different regions of the dielectric structure are assigned different coverage characteristics. The first interlayer dielectric layer provides localized coverage at the bottom steps with low side step coverage to prevent cusping, while the planarization layer provides localized coverage at the top steps with high side step coverage to achieve planarity and complete coverage.
2Manufacturing precision
If interlayer dielectric is formed with low side step coverage to prevent cusping, then cusping is avoided, but incomplete coverage of stepped structure occurs
Solution Approach 1:
The coverage requirement is segmented between two layers: the first interlayer dielectric layer covers the lower steps with low side step coverage to prevent cusping, while the planarization layer covers the upper steps and fills gaps with high side step coverage to achieve complete overall coverage.
Solution Approach 2:
The first interlayer dielectric layer is formed preliminarily to establish the base coverage and prevent cusping at critical step regions. Subsequently, the planarization layer is formed to complete the coverage and provide final planarity, ensuring both cusping prevention and complete coverage are achieved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents cusping and improves the reliability and yield of semiconductor devices by forming interlayer dielectrics with controlled step coverage, reducing defects and ensuring reliable contact formation.
Implementation Method 1
forming a first interlayer dielectric covering the stacked structure using a deposition process with a side step coverage of greater than 0 percent and less than or equal to 50 percent
Implementation Method 2
forming a second interlayer dielectric covering the first interlayer dielectric using plasma enhanced chemical vapor deposition
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a stacked structure on a substrate, forming a first interlayer dielectric covering the stacked structure, and forming a second interlayer dielectric covering the first interlayer dielectric. The stacked structure includes a stepwise shape. The first interlayer dielectric includes at least one step portion having a slope surface connecting a first top surface to a second top surface. The first top surface and the sloped surface define a first angle that is an obtuse angle. A level of the second top surface is higher than a level of the first top surface.