Interlayer Dielectric Structure to Cut Wiring Parasitic Capacitance
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Solution Overview
Problem
Existing semiconductor devices face challenges in maintaining reliability and reducing signal interference between wirings due to the use of silicon nitride layers, which increase parasitic capacitance and decrease insulation, especially as line widths are reduced for higher integration.
Innovation Solution
The semiconductor device employs a direct contact between interlayer insulating layers without silicon nitride interposition, using low-k materials like SiOCH and SiCN to minimize signal interference and enhance adhesion, while incorporating copper and diffusion barrier layers to maintain structural integrity and prevent metal elution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If silicon nitride layers are used between interlayer insulating layers, then adhesion between layers is improved, but parasitic capacitance increases and signal insulation deteriorates
Solution Approach 1:
The patent removes the silicon nitride layer from the structure, extracting the harmful element that causes parasitic capacitance while maintaining adhesion through direct contact between low-k insulating layers. This extraction eliminates the source of signal interference while preserving the necessary mechanical bonding between layers.
Solution Approach 2:
The patent changes the dielectric constant parameter by using low-k materials (SiOCH with k<3.5, SiCN with k<3.0) instead of traditional high-k silicon nitride. This parameter change reduces parasitic capacitance and improves signal insulation while the direct contact interface maintains sufficient adhesion for structural integrity.
2Productivity
If line widths are reduced for high integration, then device integration density is improved, but signal interference between wirings increases
Solution Approach 1:
The patent changes the dielectric material parameters by introducing low-k materials with reduced dielectric constants (k<3.5 for SiOCH, k<3.0 for SiCN). This parameter change directly reduces parasitic capacitance between closely spaced wirings, enabling higher integration density without proportionally increasing signal interference.
Solution Approach 2:
The patent employs composite material structures with multiple low-k layers (SiOCH and SiCN) having different dielectric properties. This composite approach allows optimization of both adhesion and signal insulation characteristics, enabling dense wiring layouts while maintaining electrical performance through the combined properties of different low-k materials.
Data Source
Figure 1
Figure 2A~2B
Figure 3A
AI summary
A semiconductor device includes a first interlayer insulating layer on a substrate and including an upper surface at a first level, a second interlayer insulating layer on the first interlayer insulating layer, and including a material with less density than that of the first interlayer insulating layer, a first contact in the first interlayer insulating layer and having an upper surface at a second level higher than the first level, a through via in the first interlayer insulating layer and substrate, and having an upper surface at a third level higher than the second level, a first wiring in the second interlayer insulating layer, in contact with the first contact, and having a lower surface at a fourth level lower than the first level, and a second wiring in the second interlayer insulating layer, in contact with the through via, and having a fifth level lower than the fourth level.