Interlayer Insulating Structure for Lower Contact Resistance

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Solution Overview

Problem

As semiconductor elements are downscaled for high integration and low power, contact resistance increases due to increased contact length, affecting element performance and reliability.

Innovation Solution

The semiconductor device incorporates a specific multilayered structure with varying thicknesses of interlayer insulating films and etching stop films, including a buffer interlayer insulating film with different thicknesses between resistance patterns and etching stop films, and uses low dielectric constant materials to reduce coupling and enhance connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the feature size of semiconductor devices is reduced to achieve high integration and low power, then integration density and power efficiency are improved, but contact resistance increases due to increased contact length

Engineering Contradiction:
Improveintegration densityVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The interlayer insulating film is divided into a first interlayer insulating film and a second interlayer insulating film with different dielectric constants. The first interlayer insulating film has a higher dielectric constant than the second, allowing for optimized electrical performance in different regions of the device structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the interlayer insulating structure are assigned different dielectric constant values. The first interlayer insulating film with higher dielectric constant is positioned in specific areas to provide enhanced electrical characteristics where needed, while the second interlayer insulating film with lower dielectric constant is used in other regions to minimize parasitic effects.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If various contact types are used for connection between wirings to achieve flexibility in design, then design adaptability is improved, but contact length increases and contact resistance worsens

Engineering Contradiction:
Improvedesign flexibilityVSAvoidcontact resistance
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces a vertical dimension to the insulating film structure by stacking first and second interlayer insulating films with different dielectric constants. This multi-layer approach provides additional degrees of freedom in optimizing electrical performance without increasing horizontal contact length.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This structure improves element performance and reliability by reducing contact resistance and maintaining electrical integrity, supporting high integration and low power requirements.

Implementation Method 1

the second interlayer insulating film includes a low dielectric constant material

Methodology Applied
Scientific EffectDielectric constant: Dielectric Permittivity

Data Source

PatentUS20250254932A1Semiconductor device
Publication Date: 2025.08.07 SAMSUNG ELECTRONICS CO LTD
  • US20250254932A1 patent drawing
  • US20250254932A1 patent drawing
  • US20250254932A1 patent drawing

AI summary

A semiconductor device includes a first connection wiring in a first interlayer insulating film, an interlayer etching stop film, a buffer interlayer insulating film, a resistance pattern, a second interlayer insulating film, a wiring via disposed in the second interlayer insulating film and penetrating the buffer interlayer insulating film and the interlayer etching stop film, wherein the wiring via contacts the first connecting wiring, a resistance via disposed in the second interlayer insulating film and contacting the resistance pattern, and a second connection wiring disposed in the second interlayer insulating film and contacting the wiring via and the resistance via. A thickness of the buffer interlayer insulating film between the resistance pattern and the interlayer etching stop film is different from a thickness of the buffer interlayer insulating film through which the wiring via penetrates.