Redundant Interlayer Signal Lines for Soft Error Resistance
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Solution Overview
Problem
Conventional semiconductor devices with dual-redundant latch circuits face deterioration in soft error resistance due to short circuits in redundant line pairs, which cannot be detected during the inspection stage, leading to undetectable anomalies and potential operational failures.
Innovation Solution
The semiconductor device incorporates a plurality of line layers with redundant line pairs disposed in different layers, where the distance between the lines is longer than the interlayer distance, reducing the likelihood of short circuits and allowing for detectable anomalies before shipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If redundant line pairs are placed close together in the same layer, then area is reduced and routing is simplified, but short circuit risk increases and soft error resistance deteriorates
Solution Approach 1:
The patent applies dimensionality change by moving redundant line pairs from the same layer to different layers (e.g., M1 and M2 layers). This spatial separation in the vertical dimension reduces the risk of short circuits while maintaining the soft error resistance function, effectively resolving the contradiction between area efficiency and reliability.
2Reliability
If redundant line pairs are placed in different layers with increased distance, then soft error resistance is improved and short circuit risk is reduced, but area increases and routing complexity increases
Solution Approach 1:
The patent utilizes vertical layering to separate redundant line pairs, achieving reliable soft error resistance without excessive area penalty. By leveraging the third dimension (layer depth), the design maintains compact horizontal footprint while ensuring adequate separation distance for reliability.
3Difficulty of detecting and measuring
If redundant line pairs are placed in different layers with increased distance, then short circuit detection capability is improved, but routing complexity increases
Solution Approach 1:
The patent simplifies short circuit detection by placing redundant line pairs in different layers where they can be independently inspected. The vertical separation makes it easier to identify and isolate potential short circuits during testing, reducing detection difficulty without requiring complex routing patterns.
Data Source
AI summary
A semiconductor device according to an aspect of the present disclosure includes: a plurality of line layers; a first line; and a second line that is not connected to the first line and is redundantly provided to transfer a signal having a level same as a level of a signal transferred through the first line. The first line and the second line are included in different layers out of the plurality of line layers, and a distance between the first line and the second line is longer than an interlayer distance between line layers next to each other out of the plurality of line layers.