Inter-layer Connection Defect Detection via Two-Port Resistance Network
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in promptly and accurately locating defects in inter-layer connections due to electromigration and stress migration, leading to prolonged test times and inefficiencies in identifying open circuits.
Innovation Solution
A method utilizing a two-port resistance network with serially connected resistance links, where each link comprises equivalent resistances and jumper resistances, allowing for the determination of defect locations by measuring actual and base input resistances and comparing them to establish a correspondence relationship, enabling faster defect detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional test methods are used to visit every node in connection links, then defect location accuracy is improved, but test time increases significantly
Solution Approach 1:
The resistance chain is divided into multiple resistance links, where each link contains inter-layer components. By measuring the total resistance of the chain and comparing it against a pre-stored correspondence relationship between resistance values and defect positions, the system can directly identify which specific link contains the defect without visiting every node individually. This segmentation approach maintains defect location accuracy while significantly reducing test time.
Solution Approach 2:
The system pre-establishes a correspondence relationship between resistance values and defect positions before actual testing. This preliminary action stores the expected resistance characteristics for different defect scenarios, enabling rapid defect identification during testing by simply comparing measured resistance against the pre-stored data, thus avoiding time-consuming node-by-node inspection.
2Measurement precision
If multiple nodes are tested individually to locate defects, then measurement precision is improved, but device complexity increases
Solution Approach 1:
Multiple resistance links are merged into a single serial resistance chain, allowing the system to test multiple inter-layer components simultaneously through one measurement. The total resistance of the chain reflects the combined state of all links, enabling defect detection across multiple components without requiring separate test infrastructure for each node, thus reducing overall device complexity while maintaining detection accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method significantly reduces the time required to locate defects in inter-layer connections, improving the efficiency and accuracy of defect identification in semiconductor testing.
Implementation Method 1
providing a test semiconductor device, wherein the test semiconductor device comprises a two-port resistance network connecting a first port and a second port of the test semiconductor device
Data Source
AI summary
A method for testing inter-layer connections is presented. The method entails: providing a test semiconductor device, wherein the test semiconductor device comprises a two-port resistance network; measuring base input resistances on at least one of the first and the second ports of the test semiconductor device for different numbers of resistance links in a defect-free circumstance; obtaining a correspondence relationship between the number of resistance links and the base input resistances; measuring actual input resistances on at least one of the first and the second ports of the test semiconductor device; and determining a position of the resistance link corresponding to the actual input resistances based on the correspondence relationship, wherein the position of the resistance link determines the location of a defect. This method can promptly locate a defect in inter-layer components and can reduce test time and simplify test procedures.