Interlayer Via Hole Formation in Embedded Circuitry Lamination
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Solution Overview
Problem
Conventional methods for fabricating interlayer conducting structures in multilayer PCBs face the risk of short circuits due to alignment offsets between lamination plates, as the conformal mask is formed before lamination, leading to potential misalignment and via hole misplacement.
Innovation Solution
A method where lamination plates are first laminated without a pre-formed laser conformal mask, and then a laser boring process is used to create via holes directly, allowing for accurate alignment and reducing the risk of short circuits without improving the interlayer offset value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conformal mask is formed prior to laminating lamination plates, then the via hole positioning is guided, but alignment offset between layers causes short circuit risk
Solution Approach 1:
The patent inverts the conventional sequence by laminating the lamination plates first and then forming the conformal mask on the already-laminated structure. This reversal eliminates the alignment offset problem because the mask is now formed after the layers are permanently bonded, ensuring the via holes are positioned accurately relative to the stop pads without being affected by lamination alignment variations.
Solution Approach 2:
The patent performs the lamination action before the mask formation, which is a preliminary action that establishes the final layer positions. By completing the lamination first, the structure is fixed in its final configuration, and subsequent mask formation and via hole drilling are performed on this stable, aligned structure, preventing short circuits.
2Ease of manufacture
If lamination plates are laminated with alignment offset, then the manufacturing process is simpler, but via holes may misalign with stop pads causing short circuits
Solution Approach 1:
By inverting the sequence to laminate first and form masks later, the patent allows for simpler lamination processes without strict alignment requirements while still achieving accurate via hole positioning in the final step, thus maintaining ease of manufacture while eliminating short circuit risks.
Solution Approach 2:
The patent introduces target points as intermediaries that are formed on each lamination plate before lamination. These target points serve as registration marks that facilitate accurate alignment during lamination, allowing the process to remain simple while ensuring proper positioning. The target points act as a mediator between the simple lamination process and the precise via hole positioning requirement.
3Manufacturing precision
If conformal mask is formed before lamination, then via hole positioning is controlled, but interlayer offset leads to via hole misplacement
Solution Approach 1:
The patent resolves this contradiction by inverting the process sequence: instead of forming the conformal mask before lamination (which requires precise interlayer offset control), the mask is formed after lamination. This eliminates the need for tight interlayer offset control while maintaining via hole positioning accuracy, as the mask is now referenced to the already-laminated structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the risk of short circuits between layers by allowing for precise laser boring after lamination, maintaining the alignment offset without requiring pre-lamination mask formation, thus ensuring reliable interlayer connections.
Implementation Method 1
a laser boring process is executed to bore from the conformal mask 9 of the second lamination pate 3 through the second lamination plate 3 positioned on a stop pad of the first circuitry 7, thus forming a via hole 14
Data Source
AI summary
A method for fabricating an interlayer conducting structure of an embedded circuitry is disclosed. In accordance with the method for fabricating an interlayer conducting structure of an embedded circuitry of the present invention, there is no laser conformal mask formed prior to laminating the first and second lamination plates. Instead, after the first and second lamination plates are laminated, a laser boring process is directly conducted to form a via hole. In such a way, even when there is an offset between the first and the second lamination plates in alignment, the risk of short circuit between different layers of lamination plates can be lowered without improving an interlayer offset value.


