Interlayer Waveguide Structure for Low-Temperature BEOL Integration
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Solution Overview
Problem
Existing optical device manufacturing processes face challenges in forming waveguides during the back end of line (BEOL) processing due to high thermal budgets, which can impact the formation of optical interconnects and increase signal loss.
Innovation Solution
The implementation of optical devices with interlayer waveguide structures that utilize low loss deposition processes, such as plasma-enhanced chemical vapor deposition (PE-CVD) at temperatures below 400°C, to form inner cores of waveguides between conductive lines during BEOL processing, enabling hybrid bonding for high-speed optical and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional high-temperature deposition processes are used to form waveguides during BEOL processing, then the waveguide formation is achieved, but signal loss increases and manufacturing efficiency decreases
Solution Approach 1:
The patent applies parameter changes by transitioning from conventional high-temperature deposition processes to low-temperature processes below 400°C. This temperature parameter change enables waveguide formation without causing signal loss while maintaining manufacturing efficiency during BEOL processing.
Solution Approach 2:
The patent replaces conventional thermal deposition mechanisms with plasma-enhanced chemical vapor deposition (PE-CVD), which operates at lower temperatures. This substitution of the deposition mechanism eliminates the need for high-temperature processing, thereby reducing signal loss while maintaining ease of manufacture.
2Reliability
If waveguides are formed between conductive lines during BEOL processing, then optical interconnectivity is achieved, but thermal budget constraints are violated
Solution Approach 1:
The patent changes the temperature parameter of the deposition process to operate below 400°C, which is compatible with the thermal budget constraints of BEOL processing. This parameter change enables waveguide formation between conductive lines without violating temperature limits.
Solution Approach 2:
The patent uses plasma-enhanced chemical vapor deposition as an intermediary process that bridges the gap between forming waveguides and maintaining thermal budget constraints. This intermediary deposition method enables optical interconnectivity while respecting temperature limits.
3Speed
If hybrid bonding is implemented for high-speed connectivity, then optical and electrical connectivity are achieved, but process complexity increases
Solution Approach 1:
The patent merges optical waveguide formation with existing BEOL processing steps, combining multiple functions into a single integrated process flow. This merging approach enables hybrid bonding for high-speed connectivity while minimizing process complexity by utilizing existing manufacturing infrastructure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively addresses the challenges of integrating waveguides between conductive lines by using low loss deposition processes, enhancing manufacturing efficiency and reducing signal loss.
Implementation Method 1
The implementation of optical devices with interlayer waveguide structures that utilize low loss deposition processes, such as plasma-enhanced chemical vapor deposition (PE-CVD) at temperatures below 400°C
Implementation Method 2
The cladding structure helps to confine optical signals within the inner core by total internal reflection... when an optical signal traveling in a waveguide is incident on the boundary between the inner core and the cladding structure at an angle exceeding the critical angle, the optical signal can exhibit total internal reflection
Data Source
AI summary
A system includes an optical device. The optical device includes a first device section corresponding to a first metallization level including at least a first conductive line located at a first plane, a second device section corresponding to a second metallization level including at least a second conductive line located at a second plane different from the first plane, and a first waveguide including a first inner core located at a third plane between the first plane and the second plane.