Interlayer Wiring Isolation via Etch Stop Masking
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Solution Overview
Problem
As semiconductor devices become more highly integrated and densely arranged, it becomes increasingly difficult to form wiring structures on a semiconductor substrate without short-circuiting or having electrically open portions, which affects the reliability of the interlayer wiring structures.
Innovation Solution
A method is developed for fabricating semiconductor devices by forming a first interlayer insulating layer and a conductive contact plug, followed by a second interlayer insulating layer and interlayer wiring that overlaps the contact plug, with etching processes using the wiring as a mask to expose and separate the contact plug, and forming a third interlayer insulating layer to cover the wiring, thereby maintaining electrical isolation and preventing unintended connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wiring structures are formed to connect various devices, then electrical connectivity is improved, but the risk of short-circuiting and electrically open portions increases
Solution Approach 1:
The patent introduces an etch stop layer positioned between the interlayer insulating layer and the contact plug. This intermediary layer prevents direct contact between the wiring structure and the contact plug during etching processes, thereby eliminating the risk of short-circuiting while maintaining electrical connectivity through proper isolation
Solution Approach 2:
The patent segments the insulating structure into multiple layers: an interlayer insulating layer and a separate etch stop layer. This segmentation allows independent optimization of each layer's function - the interlayer insulating layer provides electrical isolation while the etch stop layer prevents harmful etching penetration, thereby reducing both short-circuiting and electrically open portions
2Adaptability or versatility
If semiconductor devices are highly integrated and densely arranged, then device functionality is improved, but wiring formation difficulty increases
Solution Approach 1:
The etch stop layer is formed in advance before the wiring structure is created. This preliminary action establishes a protective barrier that prevents etching damage during subsequent wiring formation processes, making high-density wiring fabrication easier and more reliable
Solution Approach 2:
The etch stop layer acts as a mediator between the densely packed devices and the wiring structures. It enables precise wiring formation in high-density configurations by preventing unintended etching interactions while maintaining the required electrical connections
Data Source
AI summary
Semiconductor devices and methods of fabricating the same are disclosed. The methods include forming a first interlayer insulating layer and a conductive contact plug that penetrates the first interlayer insulating layer, forming a second interlayer insulating layer and a first interlayer wiring on the first interlayer insulating layer. The first interlayer wiring penetrates the second interlayer insulating layer and overlaps the first metal contact plug. The second interlayer insulating layer is etched using the first interlayer wiring as a mask until the first metal contact plug is exposed, and an exposed portion of the conductive contact plug is etched using the first interlayer wiring as the mask.