Interleave Address Generator Circuit for Burst Error Distribution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Communications channels face challenges in correcting burst errors due to noise, which can result in increased bit error rates, especially in channels using iterative decoding techniques like LDPC codes, as burst errors often affect large consecutive symbols, making error correction difficult.
Innovation Solution
An interleave address generation circuit utilizing linear feedback shift registers generates pseudorandom addresses to permute data blocks, effectively distributing burst errors across multiple codewords, thereby facilitating error correction by mapping bits from a first domain to a second domain in a subword basis, using circulant and sub-circulant addresses to ensure even distribution of parity bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interleaving is used to distribute burst errors, then error correction capability is improved, but device complexity increases due to the need for complex address generation circuits
Solution Approach 1:
The address generation circuit is segmented into multiple independent linear feedback shift registers (LFSRs), each responsible for generating specific portions of the interleaved address. This segmentation allows the complex address generation function to be divided into simpler, parallel-operating modules that are easier to implement and maintain while achieving the desired error distribution.
Solution Approach 2:
The patent replaces complex mechanical/address-based interleaving mechanisms with a mathematical approach using linear feedback shift registers to generate pseudo-random addresses. This substitution simplifies the hardware implementation by using well-understood LFSR circuitry instead of complex address calculation logic, reducing device complexity while maintaining reliability.
2Reliability
If iterative decoding techniques like LDPC codes are used to correct burst errors, then error correction performance is improved, but the difficulty of detecting and measuring burst errors increases
Solution Approach 1:
The interleaver performs preliminary action by redistributing burst errors into isolated bit errors across multiple codewords before the iterative decoding process begins. This preliminary error distribution makes the errors more detectable and correctable during the iterative decoding phase, as the decoder can more easily identify and correct isolated errors rather than concentrated burst errors.
Solution Approach 2:
The interleaver acts as an intermediary between the burst error-prone channel and the iterative decoder. It transforms the burst error pattern into a more manageable error distribution pattern, serving as a mediator that converts difficult-to-detect burst errors into easier-to-correct isolated errors without requiring the decoder to directly handle burst error detection.
3Productivity
If burst errors are concentrated in large numbers of consecutive symbols, then communication efficiency is improved, but error correction capability deteriorates
Solution Approach 1:
The interleaver applies local quality by treating different portions of the data stream differently through position-dependent permutation. Each bit position in the original stream is mapped to a different position in the interleaved stream based on pseudo-random address generation, creating locally optimized error distribution patterns that enhance error correction capability while maintaining overall communication efficiency.
Data Source
AI summary
An interleave address generation circuit includes a plurality of linear feedback shift registers operable to generate addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis. The interleave address generation circuit is operable to generate the lane addresses for each subword and the linear feedback registers configured to generate circulant addresses and sub-circulant address to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain.