Interleave Circuit Addressing for High-Throughput Block Reordering
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Solution Overview
Problem
Conventional error correction techniques in Quantum Key Distribution (QKD) face challenges with reduced throughput and difficulty in circuit implementation due to non-uniform error rates and block errors, especially when dealing with large block sizes.
Innovation Solution
An interleave circuit and communication device are designed with a reordering circuit and address calculation circuit to reorder data within a block of a predetermined size, using a double buffer operation and efficient address calculation to maintain throughput while suppressing reductions, even with large block sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If block interleave processing is performed with large block sizes to improve error correction stability, then error correction reliability is improved, but throughput is reduced
Solution Approach 1:
The interleave circuit divides the block interleave processing into multiple stages using multiple delay elements arranged in parallel. Each delay element processes a portion of the data in parallel, allowing large block processing to be achieved without sequentially processing all bits, thereby maintaining throughput while ensuring proper interleaving for error correction stability.
Solution Approach 2:
The circuit uses configurable delay elements with adjustable delay periods that can be dynamically set based on the block size and error rate conditions. This allows the system to adapt the processing depth and parallelism dynamically, optimizing both throughput and error correction reliability for different operating conditions.
2Stability of the object's composition
If block interleave processing is performed with large block sizes to reduce non-uniform error rates, then error distribution uniformity is improved, but device complexity increases
Solution Approach 1:
The circuit segments the interleaving function into multiple identical delay elements that can be implemented using standard logic circuits. This modular segmentation allows complex large-block interleaving to be built from simple, repeatable units, reducing overall circuit complexity while achieving uniform error distribution through proper parallel processing.
Solution Approach 2:
The delay elements are designed with configurable delay periods that can be adjusted based on block size requirements. By changing the delay parameter rather than redesigning the entire circuit architecture, the system achieves adaptability for different block sizes with minimal complexity increase.
Data Source
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AI summary
According to an arrangement, an interleave circuit includes a reordering circuit (110) and an address calculation circuit (120). The reordering circuit (110) is configured to, for each cycle, receive in parallel input data containing n (n is an integer of 2 or more) bits, and reorder n-pieces of the input data input in n cycles into n-pieces of output data each containing n bits input in cycles different from each other. The address calculation circuit (120) is configured to calculate write addresses for writing the n-pieces of output data into a first storage device (130a, 130b) and read addresses for reading out the n-pieces of output data from the first storage device (130a, 130b).