Interleaved 3D On-Chip Inductors Reducing Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing on-chip inductors and transformers face challenges with large size, high parasitic capacitance, low self-resonating frequency, and high electrical coupling due to vertical alignment of windings, which limits their performance and efficiency in silicon-based integrated circuits.
Innovation Solution
The implementation of interleaved 3D on-chip differential inductors and transformers, where windings are separated both vertically and horizontally across multiple layers, reducing parasitic capacitance and increasing magnetic coupling, achieved through the use of standard CMOS, BiCMOS, and SiGe technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If windings are vertically aligned to achieve compact size, then area is reduced, but parasitic capacitance increases and self-resonating frequency decreases
Solution Approach 1:
The patent transitions from planar 2D winding layouts to 3D interleaved structures across multiple metal layers. Windings are distributed vertically across different layers with alternating patterns, converting a single-plane problem into a multi-dimensional solution that reduces parasitic capacitance while maintaining compact footprint.
Solution Approach 2:
The inductor structure is segmented into multiple partial windings distributed across different metal layers. Each layer contains alternating sections of different windings (e.g., W1, W2, W3, W4 on layers 1-4), creating a segmented interleaved pattern that reduces electrical coupling and parasitic effects compared to concentrated vertical alignment.
2Device complexity
If multiple windings are placed on the same layer to simplify structure, then device complexity is reduced, but size increases and self-resonant frequency decreases
Solution Approach 1:
The patent utilizes the vertical dimension by distributing windings across multiple metal layers instead of confining all windings to a single layer. This 3D arrangement achieves compact size while the systematic interleaved pattern across layers maintains manageable structural complexity through regular alternating sequences.
3Area of stationary object
If windings are vertically aligned to achieve compact layout, then area is reduced, but magnetic coupling decreases and electrical coupling increases
Solution Approach 1:
The winding structure is segmented into alternating sections across multiple layers (W1-W4 on layers 1-4), creating an interleaved pattern that spatially separates adjacent windings. This segmentation reduces direct electrical coupling through capacitance while maintaining magnetic coupling through the shared magnetic flux path in the interleaved configuration.
Solution Approach 2:
By distributing windings vertically across multiple metal layers in an alternating interleaved pattern, the patent optimizes the spatial relationship between windings. This 3D arrangement enhances magnetic coupling efficiency while reducing unwanted electrical coupling, achieving superior performance compared to planar vertical alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design results in smaller size, higher self-resonating frequencies, increased mutual inductance, higher coupling efficiency, and improved quality factor, enabling efficient operation at higher frequencies while minimizing chip real estate and reducing phase mismatch errors.
Implementation Method 1
increased mutual inductance, higher coupling efficiency
Implementation Method 2
reducing parasitic capacitance
Data Source
AI summary
Interleaved three-dimensional (3D) on-chip differential inductors 110, 120 and transformer 100 are disclosed. The interleaved 3D on-chip differential inductors 110, 120 and transformer 100 make the best use of multiple metal layers in mainstream standard processes, such as CMOS, BiCMOS and SiGe technologies.