Interleaved ADC Arbitration for Deterministic PMIC Measurements
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Solution Overview
Problem
Existing power management integrated circuits (PMICs) face challenges in meeting high-speed and low-noise measurement specifications due to inefficiencies in arbitration methods, leading to latency and non-deterministic sample timing for critical system measurements.
Innovation Solution
A dual-arbitration scheme with an inner loop for critical measurements and an outer loop for client measurements, combined with interleaved sample accumulation and hardware settling delays, ensures deterministic update rates and high accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single arbitration method is used for ADC measurements, then the device complexity is reduced, but the measurement precision and update rate consistency deteriorate due to non-deterministic sample timing
Solution Approach 1:
The arbitration system is segmented into two independent arbitration circuits: a first arbitration circuit for critical measurements and a second arbitration circuit for client measurements. Each arbitration circuit independently manages its own measurement requests, ensuring deterministic timing for critical measurements while allowing flexible access for client measurements. This segmentation resolves the contradiction by maintaining simple individual arbiters while achieving overall deterministic sample timing through the divided architecture.
2Productivity
If multiple measurements are performed in parallel, then the productivity increases, but the measurement precision deteriorates due to noise and resource contention
Solution Approach 1:
Measurements are segmented into two priority categories handled by separate arbitration circuits. Critical measurements are processed with highest priority through the first arbitration circuit, ensuring they receive adequate resources and timing for high precision. Client measurements are handled by the second arbitration circuit, allowing parallel processing that increases overall throughput without interfering with critical measurement precision.
Solution Approach 2:
Different quality levels of service are provided to different measurement types. Critical measurements receive deterministic timing, higher priority arbitration, and guaranteed resource allocation for high precision. Client measurements receive best-effort service with flexible timing, allowing parallel execution that boosts productivity without compromising the precision of critical measurements.
3Measurement precision
If critical measurements are prioritized, then the measurement precision for critical signals improves, but the productivity for client measurements deteriorates due to limited ADC availability
Solution Approach 1:
The measurement system is segmented into two independent arbitration domains. The first arbitration circuit exclusively manages critical measurements, guaranteeing they receive the ADC with deterministic timing and highest precision. The second arbitration circuit manages client measurements, allowing them to utilize the ADC during periods when critical measurements are not active. This segmentation resolves the contradiction by ensuring critical measurements maintain high precision while client measurements achieve acceptable throughput through the separate arbitration channel.
4Device complexity
If the ADC is shared among multiple clients, then the device complexity is reduced, but the loss of time increases due to arbitration latency and non-deterministic access
Solution Approach 1:
The single ADC resource is shared through two segmented arbitration circuits that operate with different priority levels. Critical measurements are granted immediate access through the first arbitration circuit with deterministic timing, minimizing latency for time-sensitive operations. Client measurements access the ADC through the second arbitration circuit with best-effort scheduling, allowing the single ADC to serve multiple clients without excessive complexity while maintaining acceptable latency for non-critical measurements.
Data Source
AI summary
Certain aspects of the present disclosure are directed towards an apparatus for analog-to-digital conversion. The apparatus generally includes: arbitration circuitry including a first arbiter circuit comprising at least one input coupled to at least one first measurement request interface, and a second arbiter circuit comprising a first input coupled to an output of the first arbiter circuit and at least one second input coupled to at least one second measurement request interface; and an analog-to-digital converter (ADC) coupled to the arbitration circuitry and comprising a control input coupled to an output of the second arbiter circuit.


