Time-Interleaved ADC Timing Calibration for Blocker Cancellation
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Solution Overview
Problem
Time interleaved analog-to-digital converters (ADCs) in communication systems suffer from timing mismatches that generate undesirable blocker signals, degrading system performance, and existing methods fail to effectively compensate for these mismatches without requiring complex analog or timing circuitry.
Innovation Solution
A method and system that utilize a symmetric adaptive decorrelation algorithm to estimate and compensate for timing mismatches in time interleaved ADCs by determining complex coupling coefficients between desired and blocker signals, allowing for cancellation of blocker signals in the digital domain using multi-tap filters or multipliers, without the need for complex analog circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If time interleaved ADCs are used to increase sampling rate, then productivity is improved, but timing mismatches generate blocker signals that degrade signal quality
Solution Approach 1:
The patent replaces complex analog timing correction circuitry with digital signal processing. Specifically, it uses digital filters and adaptive algorithms to estimate and compensate for timing mismatches between interleaved ADC channels, substituting mechanical/analog timing adjustment mechanisms with software-based correction methods that achieve the same goal of eliminating blocker signals while maintaining the high sampling rate capability
Solution Approach 2:
The patent changes the timing parameters of the ADC channels by estimating the actual timing offsets between interleaved channels and applying compensation filters that adjust the phase and timing of each channel's output. This allows the system to operate with imperfect hardware timing while achieving accurate synchronized conversion through digital parameter adjustment
2Object-affected harmful factors
If complex analog circuitry is used to compensate for timing mismatches, then signal quality is improved, but device complexity increases
Solution Approach 1:
The patent replaces complex analog timing correction circuitry with digital signal processing. Specifically, it uses digital filters and adaptive algorithms to estimate and compensate for timing mismatches between interleaved ADC channels, substituting mechanical/analog timing adjustment mechanisms with software-based correction methods that achieve the same goal of eliminating blocker signals while maintaining the high sampling rate capability
Solution Approach 2:
The patent creates a digital model or representation of the timing mismatch characteristics by estimating coupling coefficients between channels. Instead of physically measuring and adjusting analog timing, the system creates a digital copy of the timing error characteristics and uses this model to synthesize compensation signals that cancel out the blocker effects
3Device complexity
If timing mismatch compensation is not applied, then device complexity is reduced, but aliasing effects increase and signal quality deteriorates
Solution Approach 1:
The patent implements a selective compensation approach where full timing correction is applied only to the extent necessary to eliminate blocker signals within the band of interest. The adaptive filtering applies correction selectively to frequency components where timing mismatches cause problems, rather than uniformly correcting all frequency ranges, thus achieving adequate aliasing reduction without excessive computational complexity
Data Source
AI summary
Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.