Interleaved ADC Bandwidth Calibration via Bulk Voltage Control
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Solution Overview
Problem
Interleaved analog-to-digital converters face challenges in calibrating sub-converters to correct mismatches without introducing noise or disrupting operation, particularly due to PVT variations, which affects sampling frequency and quality.
Innovation Solution
A calibration circuitry that adjusts the bulk voltage of transistors in sub-converters, using a control circuit to generate signals based on comparisons of test data from multiple sub-converters, allowing for bandwidth adjustment and calibration without interrupting the ADC's operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a calibration phase is provided for each sub-converter to correct mismatches, then the matching between sub-converters is improved, but the sampling frequency is reduced or operation is interrupted
Solution Approach 1:
The patent applies preliminary action by performing calibration measurements during idle time periods before the actual high-speed sampling operation. Test data is collected from sub-converters during periods when they are not performing primary conversion functions, allowing calibration calculations to be prepared in advance without impacting the main sampling operation's frequency or continuity.
Solution Approach 2:
The patent implements periodic action by alternating between calibration measurement phases and normal sampling phases. The system periodically switches to a calibration mode where test signals are applied to measure sub-converter characteristics, then switches back to normal operation. This periodic alternation allows calibration to occur without permanently reducing the sampling frequency during the primary conversion function.
2Measurement precision
If calibration is performed to correct PVT variations, then the quality of digital output is improved, but noise may be introduced
Solution Approach 1:
The patent extracts the calibration measurement function from the normal sampling path by using separate test signal inputs and dedicated calibration phases. This separation allows calibration measurements to be performed on sub-converters without injecting test signals into the normal signal path, thereby preventing noise introduction to the primary conversion operation while still achieving accurate calibration for improved output quality.
Solution Approach 2:
The patent uses an intermediary approach by introducing test signal generators and separate measurement paths that act as mediators between the calibration function and the sub-converters. These intermediary components allow calibration measurements to be performed without directly interfering with the normal signal flow, thus improving output quality through accurate calibration while avoiding noise contamination of the primary signal path.
3Ease of manufacture
If the sampling frequency is reduced during calibration, then sub-converters can be calibrated, but the performance of the interleaved ADC is reduced
Solution Approach 1:
The patent applies segmentation by dividing the operation of each sub-converter into distinct functional segments: calibration measurement segments and normal sampling segments. During calibration phases, sub-converters are temporarily dedicated to measurement functions with test signals applied, while during normal phases they perform primary conversion. This temporal segmentation allows calibration capability to be implemented without permanently reducing the overall performance, as each sub-converter operates at full capacity during its normal sampling segments.
Solution Approach 2:
The patent implements dynamics by making the functional state of sub-converters time-varying and adaptable. The system dynamically switches sub-converters between calibration mode and normal sampling mode based on operational requirements. This dynamic reconfiguration allows the ADC to optimize between calibration accuracy and performance on demand, rather than being locked into a fixed reduced-performance state, thereby maintaining high productivity while enabling calibration capability.
Data Source
AI summary
The present disclosure includes calibration circuitry for adjusting the bandwidth of at least one sub-converter of an interleaved analog to digital converter (ADC), the at least one sub-converter having an input switch coupled to an input line of the ADC, the calibration circuitry having a control circuit adapted to adjust a bulk voltage of a transistor forming the input switch.