Interleaved ADC Clock Delay Calibration for Timing Skew
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Solution Overview
Problem
Interleaved Analog-to-Digital Converters (ADCs) face challenges with timing skews and component mismatches, leading to spurious tones and reduced dynamic range, particularly when operating at higher sampling rates with multiple channels.
Innovation Solution
A calibration method using programmable delays and Successive-Approximation-Register (SAR) delay elements, combined with product derivative correlators and matrix processors, is employed to adjust sampling clock phases and compensate for timing differences among channels, reducing spurious tones and improving sampling accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple ADC channels are interleaved together to achieve higher sampling rates, then the sampling rate is improved, but timing skews and component mismatches among channels cause spurious tones and reduced dynamic range
Solution Approach 1:
The patent implements variable, programmable delay elements that can adjust the sampling timing of each channel independently. These delay elements allow dynamic modification of sampling parameters to compensate for timing skews and pulse-width mismatches among interleaved channels, thereby reducing spurious tones while maintaining high sampling rates
Solution Approach 2:
The patent employs calibration methods that measure timing skews and component mismatches among channels, then use this feedback information to program appropriate delay values for each channel. This closed-loop approach continuously optimizes timing alignment to minimize spurious tones and maintain measurement precision across varying operating conditions
2Measurement precision
If variable, programmable delays are added to each channel input to correct timing skews, then timing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements self-calibration capabilities where the system automatically measures its own timing skews and component mismatches, then programs the appropriate delay values without requiring external intervention. This self-service approach reduces operational complexity while achieving precise timing alignment
Solution Approach 2:
The patent performs calibration during manufacturing or initialization to pre-program delay values that compensate for timing skews and component mismatches. This preliminary action establishes optimal timing alignment before the system enters normal operation, simplifying the user interface and reducing real-time calibration complexity
Data Source
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AI summary
An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. Each channel receives a sampling clock with a different phase delay. The sampling clocks are overlapping multi-phase clocks rather than non-overlapping. Overlapping the multi-phase clocks allows the sampling pulse width to be enlarged, providing more time for the sampling switch to remain open and allow analog voltages to equalize through the sampling switch. Higher sampling-clock frequencies are possible than when non-overlapping clocks are used. The sampling clock is boosted in voltage by a bootstrap driver to increase the gate voltage on the sampling switch, reducing the ON resistance. Sampling clock and component timing skews are reduced to one LSB among all N channels.