Interleaved ADC Clock Phasing for Video Offset Compensation

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Solution Overview

Problem

Video signal processing apparatuses using interleaving analog-digital converters (ADCs) face challenges in compensating for offsets and processing high-resolution signals at high speeds.

Innovation Solution

A video signal processing apparatus is designed with two ADCs operating alternately under different clock phases in different sections of the analog video signal, with a clock generator adjusting these phases based on synchronization signals to compensate for offsets and synthesize a single digital video signal, and an adder is used to adjust the DC level and compensate for signal offsets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If interleaving ADCs are used to process high-resolution video signals, then processing speed is improved, but offset errors occur between channels

Engineering Contradiction:
Improveprocessing speedVSAvoidsignal accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent applies dynamics by making the clock phase relationship variable rather than fixed. The clock generator dynamically adjusts the phase difference between first and second clocks based on the video signal section being processed (first section vs. second section). This dynamic phase adjustment allows the system to adapt to different signal conditions and compensate for offset errors while maintaining high processing speed through interleaved ADC operation.

Inventive Principle:
Principle #15Dynamics

2Productivity

If multiple ADCs operate alternately with different clock phases, then high-speed processing is achieved, but device complexity increases

Engineering Contradiction:
Improveprocessing speedVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The clock generator serves multiple functions: it generates both the first clock and second clock signals, controls the phase differences between them, and adapts the clocking scheme based on video signal sections. This multi-functionality reduces the need for separate control circuits for each ADC, thereby managing device complexity while enabling high-speed interleaved operation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If clock phases are adjusted to compensate for offsets, then signal quality is improved, but control complexity increases

Engineering Contradiction:
Improvesignal accuracyVSAvoidcontrol complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements periodic action by alternating between two distinct clock phase configurations corresponding to first and second sections of the video signal. The clock generator periodically switches between these phase relationships, creating a rhythmic pattern of phase adjustment that simplifies control logic compared to continuous variable adjustment. This periodic approach maintains signal accuracy while reducing control complexity.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8854551B2Video signal processing apparatuses
Publication Date: 2014.10.07 SAMSUNG ELECTRONICS CO LTD
  • US8854551B2 patent drawing
  • US8854551B2 patent drawing
  • US8854551B2 patent drawing

AI summary

A video signal processing apparatus may include a first analog-to-digital converter (ADC) configured to convert an analog video signal into a first digital video signal according to a first clock; and/or a second ADC configured to convert the analog video signal into a second digital video signal according to a second clock that is different from the first clock. The first and second clocks may have a first phase difference in a first section of the analog video signal, such that the first and second ADCs operate alternately, first ADC then second ADC, and the first and second clocks may be generated to have a second phase difference, that is different from the first phase difference, in a second section of the analog video signal that is different from the first section, such that the first and second ADCs operate alternately, second ADC then first ADC.