Time-Interleaved ADC Timing With Coarse-Fine Conversion
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Solution Overview
Problem
High-speed analog to digital converters face challenges in meeting higher specification requirements for switching speed and power consumption due to shorter operating intervals, making them difficult to implement effectively.
Innovation Solution
A time-interleaved analog to digital converter design incorporating multiple coarse converter circuitries, a control logic circuit, transfer circuits, a fine converter circuitry, and an encoder circuit, which perform sequential coarse and fine conversions with noise shaping to improve signal-to-noise ratio and operational timings, thereby reducing hardware requirements and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operational speed of the analog to digital converter is increased, then the conversion speed is improved, but the operating interval becomes shorter making circuit implementation more difficult
Solution Approach 1:
The converter is divided into multiple coarse converter circuitries (first, second, third, fourth) that operate in parallel with different timing, allowing the overall conversion process to be segmented across multiple channels. This segmentation enables higher effective conversion speed without requiring each individual circuit to operate at excessively high speeds, thus reducing implementation difficulty.
Solution Approach 2:
The coarse converter circuitries operate periodically with different phase offsets, where each converter processes signals during specific time intervals. This periodic operation allows the system to achieve high average conversion speed while each individual circuit operates at manageable speeds during its active interval, reducing the complexity requirements for each circuit component.
2Productivity
If the operational speed is increased, then the conversion rate is improved, but the power consumption and switching speed requirements become higher
Solution Approach 1:
The conversion process is segmented across multiple coarse converters that share the total conversion load. Each converter operates at lower individual power levels during its active interval, but collectively they achieve high conversion rates. This segmentation distributes power consumption across multiple components rather than requiring a single high-power circuit.
Solution Approach 2:
Each coarse converter circuitry performs only a portion of the total conversion task (coarse conversion) rather than complete conversion, operating partially on the signal processing burden. This partial action reduces the power and switching speed requirements for each individual circuit while the fine converter completes the remaining work, achieving high overall productivity with reduced individual power consumption.
3Device complexity
If multiple coarse converter circuitries are used with sequential sampling, then the hardware requirements are reduced, but the timing coordination becomes more complex
Solution Approach 1:
Each coarse converter circuitry is assigned specific periodic time intervals for sampling and conversion operations, with phase offsets between different converters. This periodic scheduling simplifies timing coordination by creating a predictable, repeating pattern that can be controlled through phase-shifted clock signals, reducing the complexity of timing management despite having multiple converters.
Solution Approach 2:
The coarse converter circuitries perform preliminary coarse conversion operations during predetermined time intervals before the fine converter performs the final conversion. This preliminary action allows timing coordination to be simplified by establishing fixed phases for each converter's operation, with the control logic pre-arranged to manage the sequential flow from coarse to fine conversion across the multiple circuitries.
Data Source
AI summary
A time-interleaved analog to digital converter includes coarse converter circuitries, a control logic circuit, first and second transfer circuits, a fine converter circuitry, and an encoder circuit. The coarse converter circuitries sequentially sample an input signal and perform coarse conversions to generate decision signals. The control logic circuit generates coarse digital codes according to the decision signals. The first and second transfer circuits respectively transfer first and second residue signals. The fine converter circuitry performs a fine conversion according to a corresponding first residue signal and a corresponding second residue signal to generate a fine digital code. A sampling interval for sampling the input signal and a coarse conversion interval for performing the coarse conversion are determined based on a fine conversion interval for performing the fine conversion. The encoder circuit generates a digital output according to a corresponding coarse digital code and the fine digital code.