Time-Interleaved ADC Counter Control for Noise-Shaped Conversion

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing analog to digital converters face challenges in high-speed applications due to increased requirements for switching speed and power consumption, making it difficult to implement suitable circuits.

Innovation Solution

A time-interleaved analog to digital converter is designed using a counter control system, comprising capacitor array circuits, transfer circuits, fine converter circuitry, control circuitry, and an encoder circuit, which performs noise shaping signal conversion to improve signal-to-noise ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the operating speed of analog to digital converter is increased, then the conversion efficiency is improved, but the switching speed and power consumption requirements of circuits become higher

Engineering Contradiction:
Improveconversion efficiencyVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent divides the analog-to-digital conversion process into multiple parallel channels (first and second converter circuits), each handling a portion of the conversion task. This segmentation allows the system to achieve high conversion efficiency through parallel processing while keeping the power consumption and switching speed requirements of individual circuits manageable.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the operating speed of analog to digital converter is increased, then the conversion efficiency is improved, but the switching speed requirements of circuits become higher

Engineering Contradiction:
Improveconversion efficiencyVSAvoidswitching speed
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The conversion process is segmented into multiple parallel converter circuits, each operating at moderate switching speeds. The overall high conversion efficiency is achieved through the coordinated operation of these parallel circuits rather than requiring a single circuit to operate at extremely high switching speeds.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs periodic sampling and conversion cycles across multiple channels, where each channel processes signals in alternating time slots. This periodic action allows the system to achieve high effective conversion efficiency while maintaining manageable switching speed requirements for individual circuits.

Inventive Principle:
Principle #19Periodic action

3Measurement precision

If noise shaping signal conversion is performed on multiple signals, then the signal-to-noise ratio is improved, but the device complexity increases

Engineering Contradiction:
Improvesignal-to-noise ratioVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The noise shaping function is divided between multiple dedicated converter circuits, each responsible for processing specific signals. This segmentation of the noise shaping function across parallel circuits achieves improved signal-to-noise ratio while keeping the complexity of individual noise shaping circuits manageable.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12283969B2Time-interleaved analog to digital converter based on control of counter
Publication Date: 2025.04.22 REALTEK SEMICON CORP
  • US12283969B2 patent drawing
  • US12283969B2 patent drawing
  • US12283969B2 patent drawing

AI summary

A time-interleaved analog to digital converter includes capacitor array circuits, first and second transfer circuits, a fine converter circuitry, a control circuitry, and an encoder circuit. The capacitor array circuits sample an input signal and generate first residues according to first quantization signals. The first and second transfer circuits transfer first and second residues respectively. The fine converter circuitry performs a signal conversion on the first and second residues according to a conversion control signal to generate a second quantization signal. The control circuitry generates a count signal according to the second quantization signal, and outputs the count signal as a switching signal. The capacitor array circuits generate the second residues in response to the signal conversion, and adjusts those residues according to the switching signal. The encoder circuit generates a digital output according to a corresponding first quantization signal and the second quantization signal.