Interleaved ADC Calibration Using Dither Correlation
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Solution Overview
Problem
Interleaved analog-to-digital converters (ADCs) are sensitive to timing, gain, and bandwidth mismatches between stages, leading to inaccurate outputs due to phase and gain discrepancies, which are exacerbated at high frequencies.
Innovation Solution
A random or pseudorandom dither is injected into selected channels of the ADC, and a correlation algorithm estimates the gain experienced by the dither, allowing for comparison and adjustment of channels using analog and digital techniques to reduce mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interleaved ADC stages operate in parallel with different clock timings to increase sampling rate, then productivity is improved, but timing mismatch between stages occurs causing measurement precision degradation
Solution Approach 1:
The patent applies preliminary action by measuring and storing the actual timing, gain, and bandwidth characteristics of each ADC stage during a calibration phase before actual conversion operations. These pre-measured parameters are then used to compute correction factors that compensate for mismatches during parallel operation, allowing the system to maintain both high sampling rates and measurement precision.
Solution Approach 2:
The patent changes operational parameters by dynamically adjusting the timing offsets, gain factors, and bandwidth compensation parameters for each interleaved stage based on measured mismatch characteristics. These parameter adjustments are applied through digital signal processing to correct the output signals from each stage, thereby resolving timing and gain mismatches while maintaining high-speed parallel operation.
2Productivity
If clock phases are offset between interleaved stages to enable parallel processing, then productivity is improved, but phase mismatch increases causing measurement precision to deteriorate
Solution Approach 1:
The patent implements feedback by measuring the actual phase and timing characteristics of each interleaved stage and using these measurements to compute correction factors. The measured mismatch parameters feed into a correction algorithm that adjusts the digital output signals, creating a closed-loop system that compensates for phase errors while maintaining the benefits of parallel operation with offset clock phases.
3Measurement precision
If bandwidth mismatch occurs in RC circuits of interleaved stages, then gain mismatch and timing mismatch are produced causing measurement precision to worsen, but device complexity increases to compensate
Solution Approach 1:
The patent replaces complex analog correction circuitry with digital signal processing methods. Instead of using additional analog components to compensate for bandwidth, gain, and timing mismatches, the system measures the mismatch characteristics and applies digital correction factors to the output signals. This substitution of digital processing for analog circuitry reduces device complexity while maintaining measurement precision.
4Productivity
If multiple clock inputs with different timings are used to control parallel stages, then productivity is improved, but device complexity increases due to clock synchronization requirements
Solution Approach 1:
The patent applies preliminary action by measuring and storing the actual timing characteristics of each stage during calibration, then using these pre-measured parameters to compute correction factors. This approach eliminates the need for complex real-time clock synchronization mechanisms, as the timing mismatches are compensated through digital processing of previously measured characteristics.
Data Source
AI summary
A method and a corresponding device for calibrating an interleaved analog-to-digital converter (ADC) involve injecting a randomly determined amount of dither into at least one of a flash component and a multiplying digital-to-analog converter (MDAC) in a selected channel in the ADC. A correlation procedure is performed to estimate, based on an overall ADC output, a gain experienced by the injected dither after propagating through the channel. The injection and the correlation procedure are repeated on at least one additional channel to estimate a gain for each at least one additional channel. The estimated gains of the selected channel and the at least one additional channel are then compared to determine a degree of mismatch between the selected channel and each at least one additional channel. At least one channel is calibrated as a function of the determined degree of mismatch.