Interleaved ADC Receiver Equalization for 10G Fiber Dispersion

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Solution Overview

Problem

Implementing 10G optical communication systems over multi-mode fibers is challenging due to high dispersion and variability, requiring complex and expensive components like 10G ADCs, which are difficult to build and maintain, especially with existing materials and circuit designs.

Innovation Solution

A receiver and transceiver design featuring an interleaved ADC coupled with a multi-channel equalizer, using feedforward equalization and Viterbi decoding, along with adaptive algorithms like LMS, and incorporating open-loop amplifiers with lookup table calibration, to compensate for channel-dependent impairments and reduce complexity and cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If 10G ADCs are used to achieve high-speed data conversion, then data rate is improved, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improvedata rateVSAvoidADC complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent divides the high-speed ADC operation into multiple parallel lower-speed ADC channels that operate simultaneously. Each channel runs at a reduced data rate (e.g., 1.25 Gbps instead of 10 Gbps), but multiple channels are time-interleaved to achieve the overall 10 Gbps data rate. This segmentation reduces the complexity and cost of individual ADC components while maintaining the required high-speed performance through parallel processing.

Inventive Principle:
Principle #1Segmentation

2Speed

If complex circuit designs are used to achieve high-speed operation, then data rate is improved, but manufacturing cost increases

Engineering Contradiction:
Improvedata rateVSAvoidmanufacturing cost
Core Design Contradiction:
SpeedVSEase of manufacture

Solution Approach 1:

The patent segments the high-speed conversion task into multiple parallel lower-speed conversion channels, each using simpler circuit designs that are easier and less expensive to manufacture. The time-interleaved architecture allows standard manufacturing processes to be used for each channel while achieving aggregate high-speed performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent combines multiple parallel ADC channel outputs through time-interleaving to achieve the required 10 Gbps data rate. By merging the outputs of several lower-speed channels in a coordinated manner, the system achieves high-speed performance using components that are easier and less expensive to manufacture individually.

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If standard materials and circuit designs are used, then ease of manufacture is improved, but reliability decreases due to difficulty in building 10G components

Engineering Contradiction:
Improveease of manufactureVSAvoidcomponent reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the 10G operation into multiple parallel channels operating at lower speeds using standard materials and designs, which are more reliable. By avoiding the need to push standard components to their极限 at 10G speeds and instead using multiple channels at reduced speeds, the system achieves both ease of manufacture with standard components and improved reliability.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10841013B2High-speed receiver architecture
Publication Date: 2020.11.17 MARVELL ASIA PTE LTD
  • US10841013B2 patent drawing
  • US10841013B2 patent drawing
  • US10841013B2 patent drawing

AI summary

A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.