Interleaved ADC Edge Timing Correction for Jitter Measurement

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Solution Overview

Problem

Existing real-time digital oscilloscopes using time-interleaved analog-to-digital converters (ADCs) face challenges in accurately measuring random jitter due to interleave error, which contributes to a high jitter noise floor, despite previous methods addressing only hardware and digital signal processing adjustments that do not fully compensate for frequency-dependent timing errors.

Innovation Solution

The solution involves generating an edge location correction curve through median smoothing of time interval error measurements versus ADC sampling phase, creating a lookup table to correct timing errors, and applying this correction to each measurement, effectively separating deterministic errors from random jitter measurements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If time interleaved ADCs are used to increase sampling rate, then productivity is improved, but measurement precision deteriorates due to interleave error

Engineering Contradiction:
Improvesampling rateVSAvoidjitter measurement accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent changes the parameter of timing correction by generating an empirical correction curve based on measured time interval errors at different ADC sampling phases. This correction curve is then applied to compensate for interleave error, allowing the system to maintain high sampling rates while improving measurement precision through parameter adjustment rather than hardware modification

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces hardware-based timing adjustment mechanisms with a software-based correction approach. Instead of physically adjusting ADC timing relationships, the system uses digital signal processing to measure and correct timing errors through algorithmic compensation, substituting mechanical/hardware adjustment with computational correction

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Manufacturing precision

If hardware calibration methods are used to adjust ADC timing, then manufacturing precision is improved, but adaptability deteriorates because timing errors vary with frequency

Engineering Contradiction:
ImproveADC timing alignmentVSAvoidfrequency independence
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The patent makes the timing correction dynamic by generating correction curves for different frequency ranges. The system adapts the correction parameters based on the actual operating frequency of the signal being measured, allowing the same hardware to maintain high precision across multiple frequency conditions rather than relying on a fixed manufacturing calibration

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent performs preliminary measurement and characterization of interleave error across different frequencies to build lookup tables and correction curves before actual operation. This preliminary action enables the system to quickly apply appropriate corrections during measurement without real-time complex calculations, maintaining both speed and adaptability

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If digital signal processing correction is applied to reduce interleave error, then measurement precision is improved, but device complexity increases

Engineering Contradiction:
Improvejitter measurement accuracyVSAvoidsignal processing complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts only the essential correction information needed for jitter measurement by focusing specifically on time interval error characteristics rather than attempting to correct all aspects of the signal. This selective extraction simplifies the processing complexity while maintaining measurement precision for the specific application

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses computationally efficient correction methods that can be applied quickly and discarded for each measurement, rather than implementing complex permanent correction structures. The correction curves are generated once and reused, providing high precision without sustained computational complexity

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS7450043B2Method of compensating for deterministic jitter due to interleave error
Publication Date: 2008.11.11 TELEDYNE LECROY INC
  • US7450043B2 patent drawing
  • US7450043B2 patent drawing
  • US7450043B2 patent drawing

AI summary

A system and method for compensation of deterministic jitter in measurements made when utilizing a plurality of time interleaved analog-to-digital converters (ADCs). The system includes edge timing measurement error information for each of the plurality of time interleaved ADCs and a processing element for converting a measured edge time of one or more edges of a waveform into a corrected edge time. The processing element determines the corrected edge time by subtracting the edge timing measurement error corresponding to one or more of the time interleaved ADCs.