Time-Interleaved ADC Sampling with Derivative-Based Jitter Filtering
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Solution Overview
Problem
Sampling clock jitter and skew in time-interleaved analog-to-digital converters (ADCs) introduce errors, limiting signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR), particularly in high-bandwidth applications, due to the uncertainty in sampling instants and timing skew between channels.
Innovation Solution
A time-interleaved circuit with a differentiator and sample-selection circuit that selectively enables or disables sampling circuits based on the magnitude of the time-derivative of the input voltage, using threshold comparisons to reduce the impact of sampling clock jitter and skew by only digitizing input voltages within specified thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If ADC bandwidth and sampling speed are increased through CMOS scaling and time-interleaving, then input bandwidth and sampling speed are improved, but sampling clock jitter and skew become more significant, degrading SNR and SFDR
Solution Approach 1:
The differentiator circuit performs preliminary measurement of the input signal's rate of change before the sampling operation. By evaluating the magnitude of the derivative in advance, the system can predict whether sampling will be affected by jitter and skew, and make proactive decisions about channel selection or sampling timing to avoid degraded measurements.
Solution Approach 2:
The system uses the differentiator output as feedback to dynamically control the sampling process. The magnitude of the derivative signal feeds back to the sample-selection circuit, which adjusts channel selection or sampling timing based on real-time conditions, creating a closed-loop system that adapts to signal characteristics to minimize jitter and skew effects.
2Productivity
If time-interleaved ADC architecture is used to increase sampling speed, then productivity is improved, but timing skew between channels introduces deterministic sampling errors, degrading SFDR
Solution Approach 1:
The differentiator circuit evaluates the input signal characteristics before sampling occurs, allowing the system to pre-assess the impact of potential timing skew on SFDR. By knowing the signal's rate of change in advance, the system can select sampling channels or adjust timing to minimize deterministic errors that would degrade spurious-free dynamic range.
Solution Approach 2:
The system dynamically changes operational parameters based on signal conditions. When the differentiator detects high signal slopes, the sample-selection circuit adjusts channel selection or timing parameters to compensate for skew effects, effectively adapting the sampling process to maintain SFDR performance across varying input conditions.
3Speed
If sampling frequency is increased to meet high-bandwidth requirements, then input bandwidth is improved, but the impact of sampling jitter on SNR increases proportionally
Solution Approach 1:
The differentiator circuit performs preliminary assessment of the input signal's time-derivative magnitude before sampling. By evaluating how rapidly the signal is changing, the system can predict the sensitivity to jitter and make advance decisions about channel selection or sampling timing to minimize the impact of jitter on SNR at high bandwidths.
Solution Approach 2:
The system dynamically adjusts sampling parameters based on the differentiator's measurement of signal slope. When high-frequency components with steep slopes are detected, the sample-selection circuit modifies operational parameters to reduce jitter sensitivity, allowing the ADC to maintain SNR performance across a wide bandwidth range.
Data Source
AI summary
A derivative measurement circuit is configured to sample the input voltage of an input line to determine the time-derivative of the input voltage. A plurality of time-interleaved analog-to-digital converters (ADCs) are configured to convert respective input-voltage samples that are sampled at different times. The ADCs do not convert the input-voltage samples having respective time-derivatives that are above a predetermined threshold magnitude or that are relatively high to limit sampling clock jitter and sampling clock skew.