Time-Interleaved Integrating ADC for Low-Noise High-Rate Conversion
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face challenges with noise, quantization error, non-linearity, and high power consumption, particularly in achieving improved signal-to-noise ratios without increasing complexity or cost.
Innovation Solution
A time-interleaved integrating ADC quantizer with a single comparator and no operational amplifiers, utilizing feedback signals to reduce quantization error and improve linearity, achieves a signal-to-noise ratio comparable to higher-order sigma-delta ADCs with fewer components and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If higher-order sigma-delta ADC architectures are used to improve signal-to-noise ratio, then signal quality improves, but device complexity and power consumption increase
Solution Approach 1:
The patent divides the conversion process into multiple time-interleaved integrating stages, each handling a portion of the conversion task. This segmentation allows achieving high-order filtering effects through time-domain multiplication rather than requiring a complex high-order sigma-delta architecture, thereby improving signal-to-noise ratio while keeping individual stage complexity low
Solution Approach 2:
The patent employs periodic switching between multiple integrating converters operating in parallel with time-interleaved architecture. By periodically alternating the operation of multiple first-order integrators, the system achieves the cumulative filtering effect of higher-order systems without the complexity of true high-order sigma-delta circuits
2Measurement precision
If higher-order sigma-delta ADC architectures are used to improve signal-to-noise ratio, then signal quality improves, but power consumption increases
Solution Approach 1:
The conversion function is segmented across multiple simple first-order integrating converters operating in parallel, rather than using a single complex high-order sigma-delta converter. This distribution of functionality reduces the power burden on any single component while achieving the cumulative signal-to-noise performance of a higher-order system
Solution Approach 2:
The patent uses multiple simple, low-power first-order integrating converters that can be rapidly switched between, rather than one expensive, high-power high-order sigma-delta converter. The simple integrators consume minimal power individually, and their parallel operation with time-interleaving achieves high performance without proportional power increase
3Device complexity
If time-interleaved integrating ADC quantizer is used to reduce component count, then device complexity reduces, but conversion rate may be affected
Solution Approach 1:
The patent uses periodic switching between multiple integrating converters operating in parallel, where each converter handles a time slice of the conversion task. This time-interleaved periodic operation maintains high conversion rates by ensuring that while one integrator is settling, another is ready to accept new input, effectively multiplying the throughput without requiring complex high-speed components
Solution Approach 2:
The integrating converters perform preliminary integration of the input signal during their active time slices, preparing the signal for subsequent processing. This preliminary action allows the system to maintain high conversion rates by having converters pre-processed signals ready for the next stage, eliminating the need for complex high-speed processing in later stages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively doubles conversion rate, reduces quantization noise, and maintains or improves signal quality with reduced component count and power usage, equivalent to a fourth-order sigma-delta ADC.
Implementation Method 1
a capacitor C charges to VIN
Implementation Method 2
the capacitor discharges linearly
Data Source
AI summary
An analog-to-digital converter (ADC) comprises a plurality of time-interleaved integrating ADCs having feedback from an integrated output signal. In variations, the time-interleaved integrating ADCs have feedback compensation from at least one measure of quantization error. The time-interleaved integrating ADCs may also share a single comparator and may also share a single current source.