Time-Interleaved ADC Calibration Using Correlation and Matrix Processing
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (TIADCs) face challenges due to mismatches in clock shifts and gains between converters, leading to spurious spectral lines that can disturb signals, particularly in high-frequency and high-resolution applications like cable TV and satellite communications.
Innovation Solution
A method and device for processing sampled signals to estimate and correct clock shift mismatches and gain variations between TIADCs, allowing for direct compensation without feedback loops or calibration phases, using correlation and matrix processing to derive shift coefficients and equalize mean powers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If time-interleaved converter structures are used to increase global sampling frequency, then sampling rate is improved, but spurious spectral lines are generated due to clock shift mismatches
Solution Approach 1:
The patent uses the spurious spectral lines generated by timing skew mismatches as a diagnostic tool. By analyzing these harmful spectral components, the system estimates the timing skew values and applies corrective delays to eliminate the mismatches, thereby converting the harmful effect into a useful calibration mechanism.
Solution Approach 2:
The patent implements a feedback mechanism where the output signal is analyzed to estimate timing skew mismatches, and correction signals are fed back to adjust the sampling clocks of individual converters. This closed-loop approach continuously compensates for timing variations, eliminating spurious spectral lines while maintaining high sampling rates.
2Measurement precision
If multiple temporally interleaved converters are used to achieve high resolution, then conversion precision is improved, but device complexity increases
Solution Approach 1:
The patent enables the time-interleaved converter system to self-calibrate by using its own output signal to estimate timing skew mismatches. The system automatically generates correction signals without requiring external calibration equipment or manual adjustment, thereby simplifying the overall device complexity while maintaining high conversion precision.
Solution Approach 2:
The patent dynamically adjusts the sampling clock phases of individual converters based on estimated timing skew values. By changing the temporal parameters (phase delays) of each converter's clock signal, the system compensates for mismatches and maintains synchronized operation, thereby preserving conversion resolution without requiring complex hardware modifications.
3Object-generated harmful factors
If clock shift compensation is applied to reduce spurious lines, then signal purity is improved, but processing time increases
Solution Approach 1:
The patent performs timing skew estimation and compensation setup during an initial calibration phase before normal operation begins. By pre-calculating and storing the correction delays for each converter, the system eliminates spurious spectral lines during normal operation without requiring continuous real-time processing, thereby minimizing time loss.
Data Source
AI summary
According to one mode of implementation, a method includes an estimation including on the one hand a correlation processing involving at least one part of the sampled signal, at least one part of at least one first signal gleaned from a derived signal representative of a temporal derivative of the sampled signal and at least one part of N partial filtered signals respectively representative of N weighted differences between N pairs of bracketing versions flanking the sampled signal, N being greater than or equal to 1. On the other hand, the estimation includes a matrix processing on the results of this correlation processing. Correction processing of the M−1 trains involves respectively M−1 second signals gleaned from the derived signal and the suite of M−1 shift coefficients.