Interleaved ADC Timing Recovery with Feedback Phase Alignment
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Solution Overview
Problem
High-speed communication systems face challenges in accurately recovering data due to variations in sampling phase of analog to digital converters, which are affected by environmental conditions such as temperature and voltage changes, leading to inaccurate data recovery.
Innovation Solution
A receiver with interlocked feedback loops that adjust the phase of sampling clocks using phase control signals generated based on timing error signals, ensuring accurate sampling phases across multiple analog to digital converters, thereby improving data recovery accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sampling phase of analog to digital converters is adjusted to improve data recovery accuracy, then measurement precision is improved, but device complexity increases due to the need for multiple clock generators and feedback circuitry
Solution Approach 1:
The patent implements feedback circuitry that receives recovered data and generates phase control signals for clock generators based on timing error detection. The feedback loop continuously monitors data recovery quality and adjusts sampling clock phases accordingly, enabling automatic compensation for phase variations without manual intervention.
Solution Approach 2:
The receiver system performs self-adjustment of sampling phases through its own feedback mechanisms. The timing error detector and phase control circuits use the received signal itself to generate correction signals, allowing the system to autonomously compensate for environmental variations without external calibration or control.
2Productivity
If multiple analog to digital converters are used to handle high data rates, then productivity is improved, but reliability deteriorates due to variations in sampling phase across converters
Solution Approach 1:
The patent divides the high-speed data conversion function into multiple parallel analog to digital converters, each handling a portion of the total data rate. This segmentation enables the system to process higher overall data rates while maintaining individual converter performance within manageable limits.
Solution Approach 2:
The patent uses feedback circuitry to equalize the sampling phases across all parallel converters by generating individual phase control signals for each converter's clock generator. This ensures all converters operate at optimal phases despite environmental variations, maintaining consistent data recovery quality across the entire system.
3Measurement precision
If phase control circuitry is added to adjust sampling clocks, then measurement precision is improved, but use of energy increases due to additional active components
Solution Approach 1:
The patent adjusts the phase parameter of sampling clocks dynamically based on detected timing errors. By changing only the phase parameter rather than replacing entire converter circuits, the system achieves high precision with minimal additional energy consumption, as phase adjustment requires only small signal modifications rather than full-signal processing.
Data Source
AI summary
A receiver having analog to digital converters with phase adjustable sampling clocks. A first analog to digital converter converts an analog signal into first digital samples under control of a first sampling clock. A first clock generator adjusts a phase of the first sampling clock based on at least one first phase control signal. A second analog to digital converter converts the analog signal into second digital samples under control of a second sampling clock. A second clock generator adjusts the phase of the second sampling clock based on at least one second phase control signal. A data decision circuit recovers data based on the first and second samples. Feedback circuitry receives the recovered data and generates at least one first phase control signal for the first clock generator and generates at least one second phase control signal for the second clock generator based on the first phase control signal.