Interleaved ADC Timing Skew Correction Using Phase-Compensated NCOs
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (ADCs) face significant performance issues due to timing skew errors, which are difficult to accurately compensate using existing techniques, especially in high-performance applications, as traditional methods either require complex analog-domain tuning or power-hungry digital blocks.
Innovation Solution
The integration of a timing skew correction function within the signal down-conversion block using a numerically controlled oscillator (NCO) allows for accurate phase compensation without adding physical hardware, leveraging existing digital functions in a digital down-converter to minimize power and complexity, and employing discrete Fourier transform-based phase error estimation for dynamic compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional analog-domain tuning is used for timing skew compensation, then timing skew correction accuracy is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent replaces the mechanical/analog-domain tuning system with a digital-domain processing system. Specifically, it substitutes analog timing skew compensation circuits with digital signal processing techniques including discrete Fourier transform-based phase error estimation and numerically controlled oscillator (NCO) based correction, thereby reducing device complexity while maintaining correction accuracy
Solution Approach 2:
The patent changes the domain of operation from analog to digital, and transforms the correction approach from direct timing adjustment to phase error compensation in the frequency domain. By estimating phase errors through discrete Fourier transform and applying corrections via NCOs, the system achieves timing skew compensation with reduced hardware complexity
2Measurement precision
If power-hungry digital blocks are used for timing skew compensation, then timing skew correction accuracy is improved, but energy consumption increases
Solution Approach 1:
The patent makes the existing digital down-converter blocks perform dual functions: both their original signal processing function and the additional timing skew compensation function. By integrating phase error estimation and correction into the existing digital down-conversion pipeline using the same hardware resources (processors, memory, arithmetic units), the system achieves accurate timing skew correction without adding power-hungry dedicated compensation blocks
Solution Approach 2:
The existing digital signal processing blocks serve themselves by simultaneously performing their primary function and timing skew compensation. The digital down-converter uses its own computational resources to estimate and correct phase errors, eliminating the need for separate power-consuming compensation hardware
3Measurement precision
If complex analog-domain tuning is used for timing skew compensation, then timing skew correction accuracy is improved, but power consumption increases
Solution Approach 1:
The patent replaces power-consuming analog tuning circuits with digital signal processing techniques that can leverage existing low-power digital infrastructure. The discrete Fourier transform-based phase error estimation and NCO-based correction are implemented using standard digital signal processing blocks that consume significantly less power than traditional analog compensation circuits
Data Source
AI summary
An interleaved analog-to-digital conversion (ADC) system may have timing errors in a time domain that is corrected using phase compensation in a phase domain. The ADC system may include sub-ADCs, each receiving a clock signal, which is associated with a representation of a timing skew value, reflecting an undesired timing error. A mixer may have sub-mixers, each receiving a sub-ADC output signal and a compensated numerically controlled oscillator (NCO) value. A combiner may combine the sub-mixer output signals. A decimator may decimate the output of the combiner. Each timing skew value is in a time domain. A compensated NCO value is determined using a respective phase skew value. Each phase skew value is an offset value in phase and is not a value in time. Each phase skew value in a phase domain compensates the respective timing skew value in a time domain. Multiple ADC systems and methods are described.