Time-Interleaved ADC Clock Path Tuning for Phase Mismatch Noise
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (ADCs) in high-data rate communication applications suffer from sample time mismatches, leading to increased noise in the output due to timing errors among channel ADCs in their architecture.
Innovation Solution
A method for phase mismatch correction in high-sample rate time-interleaved ADCs involves a phase-mismatch detector driving a control circuit for the clock generator, which includes a decimating low-pass filter and common mode logic buffer, allowing for adaptive correction of clock path delays without altering the signal path, enabling efficient noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If time-interleaved ADC architecture is used to increase sampling rate, then productivity is improved, but sample time mismatch errors increase causing higher noise
Solution Approach 1:
The patent implements a feedback mechanism where the output of the time-interleaved ADC is fed back through a phase-mismatch detector that measures timing errors. The detected phase mismatch information is then used to adjust the clock signals driving the ADC channels, creating a closed-loop system that continuously corrects timing errors and reduces noise while maintaining high sampling rates
Solution Approach 2:
The patent dynamically changes the clock signal parameters (phase and timing) based on detected phase mismatch conditions. By adjusting the clock phase shifts in response to measured timing errors, the system adapts the timing parameters to eliminate sample time mismatches between parallel ADC channels, thereby reducing noise while preserving the high-productivity time-interleaved architecture
2Object-affected harmful factors
If sample time mismatch correction is implemented, then noise is reduced, but device complexity increases
Solution Approach 1:
The patent introduces a phase-mismatch detector as an intermediary component that measures timing errors without disrupting the main signal path. This detector acts as a mediator between the ADC output and clock generator, providing error information that drives correction without requiring complex direct intervention in the high-speed signal paths, thus reducing overall system complexity while achieving noise reduction
Solution Approach 2:
The patent replaces complex high-speed digital correction mechanisms with an analog phase-mismatch detection and correction approach. By using analog phase detectors and continuous-time delay adjustment circuits instead of high-speed digital signal processing for timing correction, the system achieves effective noise reduction with simpler, lower-bandwidth circuitry that is easier to implement and control
Data Source
AI summary
A method of phase mismatch correction in high-sample rate time-interleaved analog-to-digital converters (ADC) is provided. An ADC parallel array has an output signal that is processed by a phase-mismatch detector. The detector drives a clock generator control circuit for the ADC array. The clock generator includes a common mode logic (CML) buffer, a CMOS, a non-overlapping generator, a DAC and a decimating low-pass filter. The CML receives a reference clock signal providing source line control (SLC) to the CMOS, the CMOS provides SLC to the DAC that is controlled by the filter which receives a digital control signal from the phase mismatch detector. The DAC provides a corrected timing input to the CMOS that provides the corrected timing signal to the non-overlap generator, where a delay in the clock path is modified and the signal path is unaltered.