Time-Interleaved ADC Sampling Alignment for Skew Calibration

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Solution Overview

Problem

Time-interleaved analogue-to-digital converters (ADCs) suffer from artefacts due to tolerances in analogue passive circuitry and manufacturing process variations, leading to offset, gain, and timing skew errors.

Innovation Solution

A time-interleaved analogue-to-digital converter configured for operation in both an operational mode and a calibration mode, where the second ADC samples either a first time period after the first ADC or simultaneously, allowing for adjustment of sample timings to bring ADCs closer together for accurate calibration, and optionally using external calibration signals to correct gain, offset, and timing skew.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple ADCs are arranged in parallel with different sampling instants, then throughput is improved, but measurement precision deteriorates due to offset, gain, and timing skew errors

Engineering Contradiction:
ImprovethroughputVSAvoidmeasurement precision
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by performing calibration measurements before normal operation. The system first measures offset, gain, and timing skew errors when ADCs sample simultaneously or with known timing relationships, then uses these pre-determined correction values during throughput-critical operation to eliminate measurement precision deterioration.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the timing parameter dynamically - during calibration mode, ADCs sample simultaneously or with minimal skew to enable accurate error measurement, while during operational mode, ADCs use their optimal staggered timing for maximum throughput. The system also adjusts correction parameters (offset, gain, timing) based on measured errors to compensate for precision loss.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If ADCs sample at different time instants, then throughput increases, but device complexity increases due to calibration requirements

Engineering Contradiction:
ImprovethroughputVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent performs calibration measurements in advance during a calibration mode before normal operation. This preliminary action captures all necessary correction parameters (offset, gain, timing skew) that would otherwise require complex real-time adjustments during high-throughput operation, thereby reducing operational complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent creates a simplified calibration model by having ADCs sample simultaneously or with known timing relationships during calibration mode. This copied ideal sampling scenario allows the system to measure and store correction parameters that can then be applied during actual operation, avoiding the need for complex real-time synchronization and measurement mechanisms.

Inventive Principle:
Principle #26Copying

3Measurement precision

If ADCs sample simultaneously for calibration, then calibration accuracy is improved, but throughput during calibration is reduced

Engineering Contradiction:
Improvecalibration accuracyVSAvoidthroughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent performs simultaneous sampling during a dedicated calibration mode before normal operation. This preliminary action with optimal timing alignment achieves high calibration accuracy without compromising operational throughput, since the calibration measurements are completed in advance and correction parameters are stored for use during high-speed operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic calibration by alternating between calibration mode (with simultaneous sampling for accuracy) and operational mode (with staggered sampling for throughput). This periodic switching allows the system to maintain high calibration accuracy while preserving overall system productivity through the use of pre-computed correction parameters during operational phases.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentEP4589848A1Time-interleaved analogue-to-digital converters (ADCS)
Publication Date: 2025.07.23 HAMILTON SUNDSTRAND CORP
  • EP4589848A1 patent drawingFigure 1
  • EP4589848A1 patent drawingFigure 2
  • EP4589848A1 patent drawingFigure 3

AI summary

A time-interleaved analogue-to-digital converter (1) including a first analogue-to-digital converter (2a) and a second analogue-to-digital converter (2b), each arranged to sample a respective analogue input (4) periodically and produce a respective digital output (8a, 8b) based on the sampled analogue input (4), and also including a signal interleaving portion (10), arranged to combine the digital outputs (8a, 8b) to produce a digital output signal (14). The time-interleaved analogue-to-digital converter (1) is configured for operation both in an operational mode and a calibration mode. In the operational mode, the second analogue-to-digital converter (2b) is arranged to sample the analogue input (4) a first time period after the first analogue-to-digital converter (2a) samples the analogue input (4). In the calibration mode, the second analogue-to-digital converter (2b) is arranged to sample the analogue input (4) simultaneously with the first analogue-to-digital converter (2a), or a second time period apart from a time at which the first analogue-to-digital converter (2a) samples the analogue input (4), wherein the second time period is shorter than the first time period.