Time-Interleaved ADC Self-Calibration for Sub-ADC Mismatch

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Solution Overview

Problem

Time-interleaved analog-to-digital converters (ADCs) face issues with timing skew and gain/offset mismatch among sub-ADCs due to fabrication process variations, affecting their operation speed and accuracy.

Innovation Solution

A self-calibration method for time-interleaved ADCs, which includes a calibration module that uses a switch module and a calibration engine to selectively apply reference voltage levels to sub-ADCs, calibrating pre-amplifying units based on digital values generated from amplified signals to adjust for mismatches and compensate for errors between resistor series.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If multiple sub-ADCs are used in parallel to increase operation speed, then the operation speed of the time-interleaved ADC is improved, but gain mismatch and offset mismatch among sub-ADCs occur due to fabrication process variation

Engineering Contradiction:

Improveoperation speedVSAvoidgain mismatch and offset mismatch

Core Design Contradiction:

SpeedVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by performing calibration operations before normal ADC operation. The calibration module uses switch modules to selectively connect reference voltage levels to sub-ADC inputs, and calibration engines to adjust gain and offset parameters in advance, eliminating mismatches before they affect signal conversion accuracy

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The calibration module enables self-service by allowing the time-interleaved ADC to automatically calibrate its own sub-ADCs without external intervention. The calibration engine uses the ADC's own reference voltage levels and digital value determining modules to detect and correct gain and offset mismatches internally

Inventive Principle:

Principle #25Self-service

2Speed

If multiple sub-ADCs are used in parallel, then the operation speed is improved, but timing skew problem among sub-ADCs occurs

Engineering Contradiction:

Improveoperation speedVSAvoidtiming skew

Core Design Contradiction:

SpeedVSMeasurement precision

Solution Approach 1:

The patent applies feedback by using digital value determining modules to monitor the output of each sub-ADC and feed this information back to the calibration engine. The calibration engine uses this feedback to detect timing skew and adjust the timing parameters of each sub-ADC to synchronize their operation

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS7535390B2Time-interleaved analog-to-digital converter and self-calibration method thereof

Publication Date: 2009.05.19 REALTEK SEMICON CORP

AI summary

The present invention discloses a time-interleaved analog-to-digital converter (ADC), which includes a first and a second sub-ADC and a calibration module. The calibration module includes a switch module and a calibration engine. The switch module selectively provides one of a set of reference voltage levels, which are provided by a resistor series of the first sub-ADC, onto an input signal line, which is shared by the first and the second sub-ADCs. The calibration engine calibrates pre-amplifying units of the first and the second sub-ADCs according to digital signals generated by the first and the second sub-ADCs.