Time-Interleaved ADC Layout for Skew-Balanced Signal Routing

The patent applies asymmetry by strategically placing logic circuits and intermediate connection wirings in a non-uniform distribution across the AD converter circuit units. Specifically, logic circuits are placed in different positions (first position in first unit, second position in second unit) and intermediate connection wirings are routed asymmetrically to balance transmission paths. This asymmetric arrangement compensates for the inherent transmission delay differences caused by the linear placement of converter units, thereby preventing skew while maintaining high conversion speed.

The patent segments the logic circuits and intermediate connection wirings into different groups placed at different positions within the AD converter circuit units. Instead of concentrating all logic circuits in one location, the patent divides them such that first logic circuits are placed at a first position and second logic circuits are placed at a second position, with corresponding segmentation of intermediate connection wirings. This segmentation distributes the transmission paths to achieve balanced delay characteristics while maintaining manageable circuit complexity.

The patent implements self-service by designing a configuration where the logic circuits and intermediate connection wirings automatically balance the transmission delays through their strategic placement. The system self-adjusts the transmission path lengths by placing logic circuits at different positions and routing intermediate connection wirings asymmetrically, eliminating the need for external variable delay circuits or additional skew correction mechanisms. This achieves signal transmission accuracy without increasing device complexity.