Interleaved ADC Spare-Channel Timing for Accurate Sampling

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Solution Overview

Problem

Interleaved analog-to-digital converters (ADCs) introduce sampling errors when handling symmetric or quasi-symmetric periodic signals due to differences in frequency response and non-linearity among ADCs, and randomizing ADC usage can lead to performance issues and conversion errors from idle ADC discharge.

Innovation Solution

An interleaved ADC system with a controller that increments a count value based on elapsed clock cycles and selectively adjusts the ADC selection sequence to include a spare ADC when idle duration exceeds a threshold, ensuring predictable pipeline delays and reducing errors by substituting the spare ADC into the sampling sequence.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a spare ADC is kept in reserve and randomly used to replace current ADCs in an interleaving sequence, then sampling errors due to ADC differences are reduced, but performance or accuracy issues are introduced due to idle ADC discharge

Engineering Contradiction:

Improvesampling accuracyVSAvoidconversion accuracy

Core Design Contradiction:

Measurement precisionVSReliability

Solution Approach 1:

The system performs preliminary action by tracking the idle duration of the spare ADC and substituting it into the interleaving sequence before the internal circuit discharge occurs. The controller monitors the idle time and triggers substitution when the idle duration exceeds a threshold, preventing the discharge issue from occurring in the first place

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system implements feedback by continuously monitoring the idle duration of the spare ADC and using this information to control the substitution timing. The controller adjusts the interleaving sequence based on real-time feedback about the spare ADC's idle state, ensuring substitution occurs at the optimal moment to maintain accuracy

Inventive Principle:

Principle #23Feedback

2Adaptability or versatility

If strict random use of a spare ADC is implemented, then interleaved ADC issues are addressed, but other performance or accuracy issues are introduced

Engineering Contradiction:

ImproveADC usage flexibilityVSAvoidconversion accuracy

Core Design Contradiction:

Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The system applies dynamics by transitioning from static random substitution to dynamic condition-based substitution. The spare ADC is substituted based on its idle duration state rather than purely random selection, making the system adaptive to the real-time condition of the ADC while maintaining flexibility in usage

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the parameter of substitution timing from random to condition-based on idle duration. By monitoring and responding to changes in the idle time parameter, the system optimizes when substitution occurs to balance flexibility with measurement precision

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10944414B1Method and apparatus for psuedo-random interleaved analog-to-digital converter use

Publication Date: 2021.03.09 XILINX INC

AI summary

An apparatus and method for sampling an analog signal with analog-to-digital converters (ADCs) is disclosed. The ADCs may be separated into a group of interleaved ADCs and a spare ADC. The interleaved ADCs can sample the analog signal according to an interleaving sequence. An interleaved ADC controller can monitor the inactivity of the spare ADC and can replace one of the interleaved ADCs in the interleaving sequence with the spare ADC based on the inactivity.