Time-Interleaved ADC Spectrum Correction for Gain and Phase Errors

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Solution Overview

Problem

Existing parallel, time-interleaved analog-to-digital converters (ADCs) face errors due to differences between converters and timing skew, which are not optimally corrected, especially for frequency-dependent gain and phase variations.

Innovation Solution

A method involving a parallel, time-interleaved converter system that performs Discrete Fourier Transforms (DFTs) on samples from multiple ADCs, processes these DFTs to reconstruct a spectrum covering a frequency range beyond the Nyquist limit, and corrects for gain and phase errors using a mathematical model that accounts for frequency-dependent variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If parallel, time-interleaved ADCs are used to increase sampling rate, then the Nyquist rate is increased by factor M, but errors are introduced due to differences between converters and timing skew

Engineering Contradiction:
Improvesampling rateVSAvoidconversion accuracy
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent implements a calibration process that measures the actual performance of each ADC channel and uses this feedback information to correct errors. The system measures gain, phase, and timing skew for each channel, then applies correction factors to compensate for these errors, thereby maintaining high measurement precision while operating at increased sampling rates.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the parameters of the correction process by implementing frequency-dependent gain and phase correction. Instead of using fixed correction values, the system adjusts correction parameters based on the input signal frequency, allowing accurate compensation across a wide frequency range and resolving the contradiction between high sampling rate and measurement precision.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If conventional calibration is used to correct ADC errors, then offset and gain errors are corrected, but frequency-dependent gain and phase variations are not optimally corrected

Engineering Contradiction:
Improveerror correction accuracyVSAvoidfrequency range coverage
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent makes the correction process dynamic by implementing frequency-dependent correction. The system continuously adapts correction parameters based on the actual input signal frequency, allowing optimal correction accuracy across the entire frequency range rather than being fixed at a single calibration frequency. This resolves the contradiction by making the correction system adaptable to different operating conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent performs preliminary calibration to establish baseline correction factors, then uses these as starting points for ongoing frequency-dependent correction. The system pre-measures the characteristics of each channel and uses this information to guide real-time corrections, ensuring accurate performance across varying frequencies without requiring recalibration at each frequency point.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If timing skew between clock signals is reduced, then conversion accuracy improves, but clock distribution complexity increases

Engineering Contradiction:
Improvetiming accuracyVSAvoidclock distribution system
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent measures the actual timing skew between clock signals distributed to different ADC channels and uses this feedback information to correct for the skew in the signal processing stage. Rather than attempting to physically equalize clock timing through complex distribution circuitry, the system measures and compensates for timing differences digitally, reducing clock distribution complexity while maintaining timing accuracy.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS7541958B2Error reduction for parallel, time-interleaved analog-to-digital converter
Publication Date: 2009.06.02 TERADYNE INC
  • US7541958B2 patent drawing
  • US7541958B2 patent drawing
  • US7541958B2 patent drawing

AI summary

A technique for reducing errors in a PTIC (parallel, time-interleaved analog-to-digital converter) consisting of M ADCs involves sampling an input signal with the PTIC and performing M different DFTs, one for each ADC. Elements of the M DFTs are grouped together according to frequency and multiplied by correction matrices to yield a corrected, reconstructed power spectrum for the PTIC. The technique is especially effective at removing gain and phase errors introduced by individual ADCs of the PTIC, including gain and phase errors that vary with frequency.