Interleaved ADC Timing Correction for Ethernet PHY Receivers
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Solution Overview
Problem
High-speed Ethernet receivers using time-interleaved ADCs face signal-to-noise ratio degradation due to mismatches in ADCs, leading to increased bit error rate and reduced cable reach, with existing solutions increasing system cost through frequency domain error estimation and microprocessor-based post-processing.
Innovation Solution
The implementation of an interleaving ADC timing error detector circuit that corrects time offset errors by comparing post-cursor inter-symbol interference across ADCs and applying corrections using analog delay circuits, along with gain error correction using multipliers in processing paths, without requiring FFT or microprocessor hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If time-interleaved ADC array is used to achieve high sampling rate, then sampling rate is improved, but conversion resolution deteriorates due to mismatches between ADCs
Solution Approach 1:
The patent implements feedback mechanisms through timing error detector circuits that continuously monitor and detect timing offsets between parallel ADCs. The detected error signals are fed back to adjust the sampling clocks of individual ADCs, creating a closed-loop system that maintains synchronization and minimizes resolution degradation while preserving high sampling rates.
Solution Approach 2:
The patent dynamically adjusts sampling parameters including clock timing offsets and gain factors for each ADC in the time-interleaved array. By changing these parameters based on detected errors, the system optimizes the performance of each ADC channel to maintain consistent conversion resolution across all channels while operating at high sampling rates.
2Measurement precision
If frequency domain error estimation and microprocessor-based post-processing are used to correct ADC mismatches, then conversion resolution is improved, but system cost increases
Solution Approach 1:
The patent extracts the error correction functionality from complex post-processing systems and microprocessors, implementing it instead through dedicated hardware circuits integrated directly with the ADC array. By separating and dedicating specific circuits for timing error detection and gain correction, the system achieves high resolution correction without requiring expensive general-purpose microprocessors or complex frequency domain processing.
Solution Approach 2:
The patent replaces expensive microprocessor-based correction systems with simpler, dedicated hardware circuits that perform the same error correction function. These specialized circuits use basic components like delay elements, multipliers, and combiners rather than requiring costly microprocessors, FFT engines, or complex digital signal processing resources.
3Productivity
If ADCs operate at higher sampling rates to meet Ethernet speed requirements, then productivity is improved, but signal-to-noise ratio deteriorates due to timing mismatches
Solution Approach 1:
The patent performs timing error detection and correction actions before they significantly degrade signal quality. By continuously monitoring timing offsets and applying corrective delay adjustments in real-time, the system prevents timing mismatches from accumulating and degrading the signal-to-noise ratio, thereby maintaining reliable high-speed Ethernet operation.
Data Source
AI summary
A receiver circuit includes an interleaved ADC, a first delay circuit, a second delay circuit, a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit. The interleaved ADC includes a first ADC and a second ADC in parallel. The first delay circuit delays a first clock signal provided to the first ADC. The second delay circuit delays a second clock signal provided to the second ADC. The first processing channel processes data samples provided by the first ADC, and includes a first slicer. The second processing channel processes data samples provided by the second ADC, and includes a second slicer. The interleaving ADC timing error detector circuit controls delay of the first delay circuit and the second delay circuit based on an output signal of the first slicer, and an output signal or an input signal of the second slicer.