Interleaved ADC Trigger Correction via Ring Communication

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Solution Overview

Problem

High-performance oscilloscopes face challenges in accurately triggering on high-frequency signals due to under-sampled data from interleaved Analog-to-Digital Converters (ADCs), leading to false triggers and inefficiencies in data routing and processing.

Innovation Solution

Implementing a ring communication network among digital trigger processors in each ADC data pipe, sharing hysteresis and direction information to improve trigger accuracy and reduce false triggers, while distributing the processing load to eliminate data bottlenecks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If interleaved ADCs are used to achieve higher effective sample rates, then the sample rate is improved, but the data width becomes too large to route to a centralized trigger processor

Engineering Contradiction:
Improvesample rateVSAvoiddata routing complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent divides the trigger processing function across multiple distributed trigger processors, one per ADC pipe, rather than consolidating all processing in a single centralized location. Each trigger processor handles triggering decisions for its associated ADC data independently, eliminating the need to route all interleaved data to one location while maintaining accurate triggering capability.

Inventive Principle:
Principle #1Segmentation

2Productivity

If digital triggers are placed in each ADC data pipeline, then the data processing load is distributed, but each ADC is exposed to under-sampled data causing aliasing

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidtrigger accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent implements feedback mechanisms where trigger processors share trigger state information and hysteresis levels with neighboring pipes through communication links. This allows each distributed trigger processor to access contextual information from adjacent pipes to accurately determine triggering events even when working with under-sampled data portions, preventing false triggers while maintaining distributed processing efficiency.

Inventive Principle:
Principle #23Feedback

3Ease of operation

If demultiplexers are used to deinterleave interleaved ADCs, then data routing is enabled, but practical limits are reached on the number of data pipes that can be processed

Engineering Contradiction:
Improvedata routing capabilityVSAvoiddemultiplexer complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent segments the trigger processing function across multiple independent trigger processors distributed throughout the data pipeline, eliminating the need for complex centralized demultiplexing infrastructure. Each trigger processor operates independently on its associated ADC data with minimal inter-processing communication, enabling support for many data pipes without increasing demultiplexer complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240353449A1Interleaved digital trigger correction
Publication Date: 2024.10.24 TEKTRONIX INC
  • US20240353449A1 patent drawing
  • US20240353449A1 patent drawing
  • US20240353449A1 patent drawing

AI summary

A test and measurement instrument includes an array of data pipes, in which each of the array of data pipes further includes an input coupled to an output of an interleaved Analog-to-Digital Converter (ADC), a hysteresis processor coupled to the input to receive a present pipe data value, and coupled to another hysteresis processor in the array of data pipes to receive a previous data value and a previous data direction, the hysteresis processor structured to perform a comparison of the present pipe data value to the previous data value to determine whether a magnitude of a difference between the present pipe data value and the previous data value exceeds a hysteresis value, and a pipeline trigger comparator. Methods are also described.