Interleaved ADC Video Processing With Calibration for Speed and Accuracy
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Solution Overview
Problem
Conventional video signal processing systems experience degradation in ADC performance over time, leading to reduced accuracy and speed, which affects the quality of video display in devices like TVs.
Innovation Solution
A high-speed video signal processing system is developed, incorporating multiple analog to digital converters (ADCs) with an interleaving controller that enables sequential operation and calibration loops to maintain high accuracy and speed, utilizing interleaving controls and calibration logic to compensate for ADC mismatches and errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ADCs are used in video signal processing systems, then the system can operate with simple hardware structure, but the ADC performance degrades over time leading to reduced accuracy and speed
Solution Approach 1:
The patent divides the ADC function into multiple parallel ADCs (first ADC and second ADC) that operate in an interleaved manner. Each ADC processes alternating scan lines, which distributes the conversion workload and allows individual ADCs to operate at lower speeds while achieving high overall system speed. This segmentation also enables independent calibration of each ADC, improving long-term reliability by allowing individual units to be recalibrated without affecting the entire system.
Solution Approach 2:
The patent implements calibration loops that perform preliminary calibration of each ADC using test signals before normal operation. The calibration circuit generates test signals and adjusts DAC coefficients to compensate for ADC mismatches and drift. This preliminary calibration action ensures each ADC starts with optimal performance characteristics, preventing degradation and maintaining accuracy over time.
2Speed
If high-speed ADC operation is required, then the system can process video signals faster, but the accuracy and precision of conversion deteriorate due to mismatches and errors
Solution Approach 1:
The patent implements calibration loops with feedback mechanisms that continuously monitor and correct ADC performance. The calibration circuit receives feedback from test signal conversions and adjusts DAC coefficients accordingly. This feedback system compensates for mismatches between parallel ADCs and maintains high conversion accuracy even at high operating speeds by dynamically correcting errors that would otherwise accumulate.
Solution Approach 2:
The patent changes operational parameters by using different DAC coefficients for calibrating different ADCs in the parallel array. The calibration circuit selectively applies gain and offset corrections to each ADC based on its specific characteristics. This parameter adjustment allows each ADC to be optimized for its individual performance, maintaining high precision across the entire parallel ADC system during high-speed operation.
3Productivity
If multiple ADCs are used in parallel to increase speed, then the conversion rate increases, but the system complexity and calibration requirements increase
Solution Approach 1:
The patent merges multiple ADCs into a unified parallel processing system with a single interleaved output stream. The first and second ADCs process alternating scan lines and their outputs are combined into a single video signal flow. This merging approach increases throughput by utilizing multiple converters simultaneously while managing complexity through a structured interleaving scheme that allows shared calibration resources and systematic error correction.
Data Source
AI summary
A high-speed video signal processing system, which includes a reception end for receiving analog signals; a plurality of analog to digital converters coupled to the reception end for converting analog signals received from the reception end to digital signals according to control signals; and an interleaving controller coupled to the plurality of analog to digital converters for generating the control signals to selectively enable the plurality of analog to digital converters according to a predetermined sequence.