Interleaved BCH Coding With Independent Decoding for Low-Latency Memory

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Solution Overview

Problem

Existing memory systems face challenges in achieving balanced error correction with interleaved codes, as they often result in high latency, power consumption, and complexity, particularly in portable devices where efficient error protection is needed without compromising performance.

Innovation Solution

The implementation of generalized integrated interleaved (GII) BCH codes, which use a two-layer coding scheme to provide non-uniform redundancy and self-decoding capabilities, allowing for independent correction of errors within each interleave while protecting shared redundancies, thus enhancing error correction efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If integrated interleaved codes are used for error correction, then error correction capability is improved, but latency increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The code is divided into multiple interleaves (first interleave, second interleave, etc.), each capable of independent decoding. This segmentation allows the decoding process to be parallelized, reducing overall latency while maintaining strong error correction capability across the entire code structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a two-dimensional structure with multiple interleaves and multiple generator polynomials. This dimensional expansion allows for independent processing of each interleave while maintaining overall code integrity, enabling parallel decoding operations that reduce latency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If integrated interleaved codes are used for error correction, then error correction capability is improved, but power consumption increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

By segmenting the code into independent interleaves that can be decoded separately, the patent enables selective processing. Only the necessary interleaves need to be decoded based on error patterns, reducing overall power consumption compared to decoding the entire code structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent allows for partial decoding where only specific interleaves are processed based on the actual error conditions. This partial action approach reduces power consumption by avoiding unnecessary processing of error-free data while maintaining adequate error correction capability.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If integrated interleaved codes are used for error correction, then error correction capability is improved, but device complexity increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidcomplexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the complex error correction code into multiple simpler interleaved components. Each interleave uses standard BCH encoding with its own generator polynomial, making individual components simpler while the overall structure provides enhanced error correction capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic selection of generator polynomials for different interleaves, allowing the system to adapt to different error conditions. This dynamic approach maintains manageable complexity by selecting appropriate polynomials based on the specific application requirements.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11632135B2Apparatuses and methods for interleaved BCH codes
Publication Date: 2023.04.18 MICRON TECHNOLOGY INC
  • US11632135B2 patent drawing
  • US11632135B2 patent drawing
  • US11632135B2 patent drawing

AI summary

An example methods for interleaved BCH codes can include encoding a plurality of portions of data using a first generator polynomial to obtain a plurality of respective BCH codewords. The method can include encoding an additional BCH codeword based at least in part on a second plurality of portions of data and the plurality of BCH codewords using a second generator polynomial. The method can include outputting the plurality of respective BCH codewords and the additional BCH codeword.