Interleaved Binning ROIC for High Dynamic Range Imaging
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Solution Overview
Problem
Current digital pixel Read-Out Integrated Circuits (ROICs) face limitations in achieving simultaneous high-resolution image output and two-color operation, particularly at smaller pixel sizes, due to counter rollover issues and increased power consumption, which restricts their dynamic range and scalability.
Innovation Solution
A two-stage analog to digital conversion system using coarse and fine residue conversion with cascading digital counters and compact SRAM latches enables high dynamic range and scalable two-color operation, allowing for simultaneous high-resolution and lower-resolution modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If counter latches are used for both storage and readout in existing digital pixel ROICs, then the device structure is simplified, but the time available for integration and readout is reduced, reducing sensitivity and increasing required data rates
Solution Approach 1:
The patent divides the conversion process into two separate stages: coarse conversion and fine residue conversion. This segmentation allows each stage to be optimized independently, with coarse conversion handling the bulk of the dynamic range and fine conversion providing precision, thereby resolving the conflict between simplified structure and high sensitivity
Solution Approach 2:
The patent introduces a temporal dimension by performing conversions in sequence rather than simultaneously. The two-stage conversion process occurs at different time intervals, allowing integration and readout to overlap more efficiently, thus improving sensitivity without significantly increasing structural complexity
2Device complexity
If counter latches are used for coarse conversion only, then the device structure is simplified, but the dynamic range and resolution are limited while power consumption increases
Solution Approach 1:
The conversion process is segmented into coarse conversion using counter latches and fine conversion using a separate fine conversion counter. This segmentation enables the system to achieve high dynamic range and resolution by combining the capabilities of both conversion stages, while keeping each individual stage relatively simple
Solution Approach 2:
The fine conversion counter is nested within the overall conversion architecture, operating on the residue from the coarse conversion. This nested structure allows the fine conversion to add precision without requiring a complete redesign of the coarse conversion stage, thereby achieving high measurement precision with controlled device complexity
3Measurement precision
If separate fine conversion counter is added to allow counter latches to be used for both coarse and fine conversions, then the conversion capability is improved, but pixel size and/or number of ROIC layers increases
Solution Approach 1:
The patent merges the coarse and fine conversion results through a combination logic that integrates the output of counter latches and the fine conversion counter. This merging approach allows both conversion capabilities to coexist in a compact manner, improving conversion capability while controlling pixel size through efficient space utilization
Solution Approach 2:
The patent utilizes vertical stacking of ROIC layers to accommodate the fine conversion counter and associated circuitry. By transitioning from a planar to a three-dimensional architecture, the system can improve conversion capability without significantly increasing the lateral pixel size, thus managing area constraints effectively
4Measurement precision
If stacked digital layers are used to mitigate pixel size and ROIC layer issues, then the conversion capability is improved, but fabrication and assembly costs increase significantly
Solution Approach 1:
The patent designs the fine conversion counter and associated circuitry to be integrated within the existing ROIC layer structure, allowing the same fabrication processes to be used for both coarse and fine conversion components. This multi-functional approach improves conversion capability while avoiding the need for separate stacked digital layers, thereby controlling fabrication and assembly costs
5Device complexity
If smaller geometry (e.g., 14 nm process) is used to mitigate pixel size and layer issues, then the device complexity is reduced, but fabrication costs become very expensive
Solution Approach 1:
The patent optimizes the geometry and dimensions of the fine conversion counter and associated circuitry to fit within standard pixel sizes using conventional fabrication processes. By carefully adjusting design parameters such as transistor width, length, and spacing, the system achieves compact integration without requiring expensive smaller geometry processes, thus controlling fabrication costs while managing device complexity
Data Source
AI summary
A system for providing high resolution image output for pilotage and two color operation for threat detection is disclosed. The system comprises a focal plane array comprising a plurality of pixels arranged into groups of equal numbers, wherein each pixel comprises at least two detectors for receiving electromagnetic energy and a readout integrated circuit.