Interleaved Cache Controllers with Shared Metadata Fabric
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Solution Overview
Problem
Current memory systems face inefficiencies due to limitations in interleaving memory controllers and cache controllers, leading to suboptimal performance in terms of bandwidth and latency, particularly when handling sub-OS page granularity and OS page size, which affects the overall throughput and stream bandwidth.
Innovation Solution
Implementing a metadata store fabric that allows shared distributed metadata access among multiple cache controllers, enabling efficient operation at sub-OS-page-granularity interleaving without increasing cache controller capacity, and using a mesh structure to redistribute metadata storage between cache controllers and metadata stores, allowing parallel operations without additional latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory controllers and cache controllers are interleaved at OS page size granularity, then system stability and simplicity are maintained, but bandwidth and latency performance deteriorate due to suboptimal parallel operation utilization
Solution Approach 1:
The patent divides the memory address space into sub-OS page granularity segments, allowing finer-grained interleaving between multiple cache controllers. This segmentation enables more cache controllers to operate in parallel on different segments of the same OS page, thereby increasing bandwidth without requiring complete redesign of the interleaving architecture.
Solution Approach 2:
The patent introduces a new dimension of interleaving granularity below the traditional OS page level. By operating at sub-OS page granularity, the system creates an additional layer of parallelism that allows multiple cache controllers to simultaneously access different portions of the same OS page, effectively increasing throughput without proportionally increasing controller count.
2Productivity
If cache controller capacity is increased to handle sub-OS page granularity, then performance improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the metadata storage function from individual cache controllers into a shared metadata store that is accessible by multiple cache controllers. This consolidation eliminates the need for each cache controller to maintain its own full metadata, thereby reducing the capacity requirements of individual controllers while enabling sub-OS page granularity interleaving and improving overall throughput.
Solution Approach 2:
The patent introduces a shared metadata store as an intermediary between cache controllers and the memory system. This intermediary centralizes metadata management, allowing multiple cache controllers to access and coordinate their operations on sub-OS page segments without each controller needing to store complete metadata, thus reducing individual controller capacity requirements.
3Productivity
If separate metadata stores are allocated to each cache controller, then access speed is maintained, but bandwidth is limited due to inability to share metadata for parallel operations
Solution Approach 1:
The patent creates a universal metadata store that serves multiple cache controllers simultaneously. This shared metadata store is designed to handle concurrent access requests from multiple controllers, providing both high bandwidth for parallel operations and fast access times through optimized memory architecture and access protocols that prevent bottlenecks.
4Productivity
If interleaving is implemented at sub-OS page granularity, then stream bandwidth increases, but latency increases due to additional coordination overhead
Solution Approach 1:
The patent implements preliminary action by pre-organizing memory addresses into sub-OS page granularity segments and pre-establishing the mapping between these segments and cache controllers. This pre-organization allows cache controllers to immediately begin parallel operations on sub-OS page segments without requiring runtime coordination overhead, thereby achieving high stream bandwidth without increased latency.
Data Source
AI summary
Interleaved cache controllers with shared metadata are disclosed and described. A memory system may comprise a plurality of cache controllers and a metadata store interconnected by a metadata store fabric. The metadata store receives information from at least one of the plurality of cache controllers, a portion of which is stored as shared distributed metadata. The metadata store provides shared access of the shared distributed metadata hosted to the plurality of cache controllers.