Interleaved Caches for Database Sequence Generation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In modern database systems, the increasing number of concurrent users and requests for sequence numbers leads to significant waiting times due to contention for access to sequence latches, which can exceed processing time, and existing technologies fail to efficiently generate ordered sequences using interleaved caches while maintaining low latency and sequence ordering.
Innovation Solution
The implementation of semaphore protected interleaved caches, where a predetermined sequence is divided into multiple interleaved caches, and each cache is mapped to a semaphore, with access granted using a round-robin assignment technique and atomic operations to ensure serialized access and reduce contention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single sequence latch is used to serialize requests, then sequence ordering is maintained, but waiting time increases significantly with large numbers of concurrent users
Solution Approach 1:
The patent divides the single sequence latch into multiple interleaved sequence caches, each protected by its own latch. This segmentation allows multiple users to access different caches concurrently rather than queuing for a single latch, thereby maintaining sequence ordering through round-robin allocation while significantly reducing waiting time for sequence generation.
2Productivity
If multiple interleaved caches are used to reduce waiting time, then sequence generation speed improves, but system complexity increases
Solution Approach 1:
The system is segmented into multiple interleaved caches with dedicated latches, where each cache handles a portion of the sequence space. This segmentation improves productivity by enabling parallel access while managing complexity through a systematic round-robin allocation strategy that ensures orderly sequence generation across all caches.
Solution Approach 2:
The system pre-allocates sequence ranges to different interleaved caches before users request sequences. This preliminary action populates each cache with a portion of the sequence space, allowing users to retrieve sequences immediately from their assigned cache without waiting for latch acquisition, thus improving speed while keeping the allocation logic manageable.
3Speed
If sequence ranges are pre-allocated to reduce waiting time, then access speed improves, but risk of sequence exhaustion in individual caches increases
Solution Approach 1:
The total sequence space is segmented across multiple interleaved caches, so that exhaustion of one cache does not affect others. Users can access sequences from their assigned cache at high speed, while the system as a whole maintains reliability through the distributed nature of the caches and the ability to reallocate sequences from the global pool when needed.
Solution Approach 2:
The system dynamically adjusts the sequence allocation parameters by monitoring cache exhaustion conditions and reallocating sequence ranges from the global pool to caches that are running low. This parameter change maintains both fast access speed and reliable sequence availability across all caches.
Data Source
AI summary
A method, system, and computer program product is disclosed for generating an ordered sequence from a predetermined sequence of symbols using protected interleaved caches, such as semaphore protected interleaved caches. The approach commences by dividing the predetermined sequence of symbols into two or more interleaved caches, then mapping each of the two or more interleaved caches to a particular semaphore of a group of semaphores. The group of semaphores is organized into bytes or machine words for storing the group of semaphores into a shared memory, the shared memory accessible by a plurality of session processes. Protected (serialized) access by the session processes is provided by granting access to one of the two or more interleaved caches only after one of the plurality of session processes performs a semaphore altering read-modify-write operation (e.g., a CAS) on the particular semaphore. The interleaved caches are assigned values successively from the predetermined sequence using a round-robin assignment technique.