Interleaved CDR Feedback for Precise Serial Phase Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As data transfer rates increase, processing systems face difficulties in generating and aligning a clock signal from serial data streams due to the need for complex and costly circuitry to capture and process timing information quickly, leading to inefficiencies and data distortion.
Innovation Solution
A clock and data recovery (CDR) system that includes a sampling circuit and an interleaving feedback network with delay-locked loops and multiplexers to produce high-resolution feedback signals, allowing for accurate phase-alignment of the sampling circuit with the serial data stream, reducing the need for extensive delay cells and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional feedback networks use more delay cells to achieve higher resolution phase alignment, then clock recovery accuracy improves, but device complexity and power consumption increase
Solution Approach 1:
The feedback network is segmented into multiple interleaved feedback paths, each with fewer delay cells. These paths operate in parallel to collectively provide high-resolution phase alignment. The segmentation allows each segment to use minimal delay cells while the combination achieves the desired resolution without requiring a single long delay chain.
Solution Approach 2:
The patent transitions from a single-dimensional delay chain approach to a multi-dimensional interleaved feedback structure. By introducing multiple feedback paths that are interleaved in time and phase, the system achieves high resolution in the phase domain without requiring proportional increases in the number of delay cells in each individual path.
2Productivity
If conventional feedback networks increase delay cells for high data rates, then clock recovery capability improves, but power consumption increases
Solution Approach 1:
The feedback network is divided into multiple interleaved paths, each handling a portion of the phase alignment task. This segmentation reduces the computational and energy burden on each individual path, allowing the system to support high data rates without proportionally increasing total power consumption.
Solution Approach 2:
Each interleaved feedback path uses only the necessary number of delay cells to accomplish its specific phase alignment portion, avoiding the excessive action of having all delay cells active simultaneously. This partial action approach reduces overall power consumption while maintaining the capability to handle high data rates.
3Measurement precision
If processing systems use complex circuitry to capture timing information quickly, then clock signal alignment improves, but device complexity and cost increase
Solution Approach 1:
The timing information capture function is segmented across multiple interleaved feedback paths rather than requiring a single complex circuit. Each path captures timing information for its specific phase portion, and the combined output achieves high timing accuracy with simpler individual circuits.
Solution Approach 2:
The interleaved feedback paths act as intermediaries between the serial data stream and the clock recovery function. Each path processes timing information for a specific phase interval, and the combination of these intermediary paths achieves accurate clock alignment without requiring a single overly complex circuit.
Data Source
AI summary
A clock and data recovery (CDR) system and method for recovering timing information and data from a serial data stream. The CDR system includes a sampling circuit that produces a recovered clock/data signal and an interleaving feedback network that provides feedback to the sampling circuit. The feedback network includes a logic circuit that produces control signals based on the recovered clock/data signal, a first multiplexer that selects from four phases of a global clock signal based on a control signal, a first delay-locked loop having a first set of delay cells coupled to a second multiplexer that produces a delayed signal based on the selected global clock signal, and a second delay-locked loop having a second set of delay cells that produces a set of phase-shifted feedback signals that are applied to the sampling circuit to phase-align the sampling circuit with the transitions in the received serial data stream.