Time-Interleaved Clock Averaging for Skew Suppression
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Solution Overview
Problem
Interleaved clocks in high-speed data converters suffer from clock phase mismatch, particularly as output frequency approaches the Nyquist frequency, leading to performance degradation and complex calibration processes, with existing solutions like high-speed phase detectors and injection locking oscillators having limitations such as increased loading, limited bandwidth, and difficult circuit layouts.
Innovation Solution
The proposed solution involves an averaging architecture that converts clock phase mismatch to amplitude mismatch and vice versa using amplitude regulators, such as CMOS inverters or operational amplifiers, to eliminate mismatches between interleaved clock signals, reducing the need for dedicated phase correction circuits and minimizing loading on the highest speed clock path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-speed phase detector is used to correct clock phase mismatch, then clock phase accuracy is improved, but loading on the highest speed clock path increases and clock quality degrades
Solution Approach 1:
The patent replaces the conventional high-speed phase detector (which requires heavy loading for phase detection) with a phase-to-amplitude conversion mechanism. By converting phase mismatch into amplitude mismatch that can be detected and corrected through amplitude regulation, the system eliminates the need for a dedicated high-speed phase detector, thereby reducing loading on the clock path while maintaining phase accuracy.
Solution Approach 2:
The patent changes the detection parameter from phase domain to amplitude domain. Instead of directly detecting phase mismatch, the system converts phase mismatch into amplitude mismatch through phase-to-amplitude conversion, then detects and corrects it in the amplitude domain using amplitude regulators. This parameter transformation reduces the complexity and loading requirements of the correction circuitry.
2Measurement precision
If a high-speed phase detector is used for phase correction, then clock phase mismatch is corrected, but the calibration process becomes complicated due to synchronization loop interruption
Solution Approach 1:
The patent replaces the complex phase detection and correction mechanism (which interrupts synchronization loops) with an amplitude-based correction system. The phase-to-amplitude conversion allows continuous operation without interrupting the synchronization loop, as amplitude regulation can be performed seamlessly without breaking the clock distribution synchronization.
Solution Approach 2:
The system performs self-correction through amplitude regulation without requiring external calibration interventions. The amplitude regulators automatically adjust the clock signals based on the converted amplitude mismatch, enabling the system to self-correct phase errors without complicating the calibration process or interrupting normal operation.
3Measurement precision
If device size is increased to reduce offset in phase detection, then detection accuracy is improved, but loading increases
Solution Approach 1:
The patent changes the detection domain from phase to amplitude, where amplitude regulation can be achieved with smaller device sizes and lower loading. Amplitude detection and regulation require less circuit complexity and generate less loading compared to high-speed phase detection, thus maintaining detection accuracy while reducing the device size and loading requirements.
4Measurement precision
If an injection locking oscillator is used for clock skew correction, then phase mismatch is corrected, but the circuit layout becomes difficult and systematic phase offset increases
Solution Approach 1:
The patent replaces the injection locking oscillator (which has complex layout requirements and sensitivity to systematic offsets) with a phase-to-amplitude conversion approach combined with amplitude regulation. This substitution eliminates the need for precise layout matching and reduces sensitivity to systematic phase offsets, making the circuit easier to manufacture with standard layout practices.
Data Source
AI summary
A time-interleaved clock circuit, including circuitry to provide multiple clock components of a sampling clock. The clock components are corrected by averaging pairs of the multiple clock components in order to output averaged signals. The time-interleaved clock is applied to data conversion in which input signals of the analog signal domain or of the digital signal domain are sampled based on the corrected clock components and converted to the digital signal domain or the analog signal domain, respectively.