Interleaved Clock Skewing for Low-Jitter ADC Timing
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Solution Overview
Problem
Interleaved analog-to-digital converter systems face performance degradation due to inaccurate positioning of interleaved clock signals, which introduces excessive jitter, degrading system accuracy and signal-to-noise ratio.
Innovation Solution
The use of selectively-skewed time-interleaved clock signals generated by combinations of fixed and variable clock skewers, which provide precise temporal control and reduce jitter by allowing for adjustable delays within the clock paths, ensuring accurate alignment of samples without exceeding the maximum operating rate of individual converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interleaved clock signals are used to operate at higher system rates, then productivity is improved, but measurement precision deteriorates due to inaccurate clock positioning and excessive jitter
Solution Approach 1:
The clock network is divided into multiple independent clock paths, each serving a specific converter. Each path includes dedicated skewers that can be independently adjusted, allowing precise control of timing for each interleaved channel while maintaining overall high system throughput
Solution Approach 2:
Fixed skewers provide deterministic baseline timing offsets for each clock path, while variable skewers allow fine-grained local adjustment of timing parameters. This hierarchical approach enables precise timing control tailored to each converter's specific requirements
2Measurement precision
If clock positioning is adjusted to improve timing accuracy, then measurement precision is improved, but reliability deteriorates due to excessive jitter introduced by positioning processes
Solution Approach 1:
The positioning function is segmented between fixed skewers (providing stable, deterministic offsets) and variable skewers (providing fine adjustment). This segmentation allows the system to achieve precise timing alignment without introducing excessive jitter, as each segment contributes to positioning in a controlled manner
Solution Approach 2:
Fixed skewers establish predetermined timing offsets in advance, creating a stable timing framework before variable adjustments are applied. This preliminary positioning reduces the need for large variable adjustments, thereby minimizing jitter introduction while achieving required timing accuracy
3Manufacturing precision
If variable delays are used to achieve precise clock alignment, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The clock network is segmented into fixed and variable components, where fixed skewers handle coarse timing alignment and variable skewers handle fine adjustment. This segmentation achieves high manufacturing precision while managing complexity by dividing the adjustment function across multiple simpler components
Solution Approach 2:
The clock network transitions from static fixed skewers to dynamic variable skewers that can be adjusted during operation. This dynamic capability enables precise clock alignment to be achieved and maintained despite variations in operating conditions, while the modular structure manages overall system complexity
Data Source
AI summary
Converter systems are provided that use particular combinations of fixed and variable clock skewers to generate interleaved clock signals for the systems. These combinations have been found effective in accurately generating selectively-skewed clocks while simultaneously restricting the jitter that generally accompanies the skewing process.