Interleaved Clock Signal Generator for Stable High-Frequency Testing
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Solution Overview
Problem
In integrated circuit testing, using a high-end test machine to generate a high-frequency test clock signal is costly, and existing methods for frequency multiplication result in unstable transition edges, reducing test stability and accuracy.
Innovation Solution
A clock signal generator comprising a first and second oscillator, a delay value generator, and an output clock signal generator that alternately activates the oscillators based on control signals to generate two clock signals with different phases, which are combined to produce a high-frequency output clock signal with stable transition edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-end test machine is used to generate a high-frequency test clock signal, then the test frequency is improved, but the test cost increases substantially
Solution Approach 1:
The patent divides the clock signal generation into multiple segments: a low-frequency reference clock from a general test machine, a frequency multiplication stage using a counter, and a phase stabilization stage using delay elements. This segmentation allows using a low-end test machine with additional circuitry rather than requiring an expensive high-end test machine, thereby reducing test cost while achieving high-frequency operation
Solution Approach 2:
The patent introduces intermediary components between the test machine and the DUT: a frequency counter that multiplies the reference clock frequency, and delay elements that stabilize the phase. These intermediaries enable a general test machine to effectively provide high-frequency stable clock signals without requiring the test machine itself to have high-frequency generation capability, thus avoiding substantial cost increase
2Speed
If frequency multiplication is performed using a cutting signal, then the test clock frequency is improved, but the transition edge stability deteriorates
Solution Approach 1:
The patent introduces delay elements as intermediary components between the frequency multiplication stage and the output stage. These delay elements are configured to delay the clock signal and the cutting signal by matched amounts, ensuring that the transition edges remain aligned and stable. This intermediary approach maintains transition edge stability while achieving frequency multiplication
Solution Approach 2:
The patent applies preliminary action by pre-calculating and pre-setting the delay values for the delay elements before operation. The delay amounts are determined in advance to compensate for the timing differences introduced by frequency multiplication, ensuring that transition edges remain stable without requiring real-time adjustment during operation
Data Source
AI summary
A clock signal generator and a clock signal generating method are provided. The clock signal generator is adapted for a test machine. The clock signal generator includes a first oscillator, a second oscillator, a delay value generator, and an output clock signal generator. The first oscillator and the second oscillator are activated alternatively. The first oscillator generates a first clock signal with a first frequency according to a delay value. The second oscillator generates a second clock signal with a second frequency according to the delay value, where phases of the first clock signal and the second clock signal are different. The delay value generator detects a pulse width of a reference pulse signal to generate the delay value. The output clock signal generator combines the first clock signal and the second clock signal to generate an output clock signal.