Time-Interleaved DAC Bit Swapping for Mismatch Distortion

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Solution Overview

Problem

Time-interleaved digital-to-analog converters (DACs) face distortion due to gain mismatch, offset mismatch, and timing mismatch between different DAC channels, limiting their high-speed and large bandwidth performance.

Innovation Solution

A time-interleaved digital-to-analog converter architecture that incorporates a time-domain dynamic element matching (TDEM) circuit, which generates adjusted data sequences by swapping bits between different DAC channels, thereby mitigating distortion caused by mismatches and improving the conversion process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If time-interleaved DAC architecture is used to achieve high speed and large bandwidth conversion, then conversion speed and bandwidth are improved, but distortion increases due to mismatches between different DAC channels

Engineering Contradiction:
Improveconversion speedVSAvoidsignal distortion
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies dynamic element matching by making the data sequence assignment to DAC channels dynamic rather than static. The TDEM circuit dynamically swaps data sequences between channels based on real-time performance, allowing the system to adapt to varying conditions and mitigate distortion while maintaining high conversion speed and bandwidth

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of data sequence assignment by implementing time-domain dynamic element matching. The TDEM circuit modifies which data sequences are assigned to which DAC channels over time, changing the operational parameters to optimize performance and reduce distortion caused by channel mismatches

Inventive Principle:
Principle #35Parameter changes

2Reliability

If time-domain dynamic element matching is implemented to reduce distortion, then signal quality is improved, but device complexity increases due to additional TDEM circuit

Engineering Contradiction:
Improvesignal qualityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The TDEM circuit is designed to be multi-functional, serving both as a data sequence management unit and as a distortion mitigation mechanism. By making the data sequence assignment dynamic, the same circuit structure achieves both high-speed operation and distortion reduction, reducing the need for separate correction circuits

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If multiple DAC channels are used to achieve high-speed conversion, then productivity is improved, but manufacturing precision requirements increase due to mismatch constraints

Engineering Contradiction:
Improveconversion throughputVSAvoidchannel matching precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent makes the data sequence assignment dynamic through the TDEM circuit, allowing the system to adapt to manufacturing variations in DAC channels. Instead of requiring precise static matching, the dynamic swapping mechanism compensates for mismatches, enabling high productivity with relaxed manufacturing precision requirements

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10958284B2Time-interleaved digital-to-analog converter with time-domain dynamic element matching and associated method
Publication Date: 2021.03.23 MEDIATEK INC
  • US10958284B2 patent drawing
  • US10958284B2 patent drawing
  • US10958284B2 patent drawing

AI summary

A time-interleaved digital-to-analog converter (DAC) includes a digital processing circuit, a time-domain dynamic element matching (TDEM) circuit, a plurality of DACs, and a combining circuit. The digital processing circuit generates data sequences according to the digital signal. The data sequences include a first data sequence and a second data sequence. The TDEM circuit swaps a portion of the first data sequence with a portion of the second data sequence to generate a first adjusted data sequence and a second adjusted data sequence. The DACs include a first DAC and a second DAC. The first DAC has a first DAC cell that operates in response to the first adjusted data sequence. The second DAC has a second DAC cell that operates in response to the second adjusted data sequence. The combining circuit generates the analog signal by combining analog outputs of the DACs.