Interleaved DAC Switching for High-Bandwidth Analog Signals
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Solution Overview
Problem
Existing digital-to-analog conversion technologies face challenges in achieving high-bandwidth analog signals due to limitations in analog bandwidth and sensitivity to imperfections in analog multiplexer matching.
Innovation Solution
The mechanism employs a controlled switch with N inputs and a single output, where N sub-streams of analog samples are processed to generate a high-bandwidth analog signal. This is achieved by intentionally capturing data transitions between adjacent analog samples, resulting in an effective sampling rate twice that of the number of sub-streams, using a control signal with a period of ~2NTs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional analog multiplexers are used to combine sub-DAC outputs, then signal bandwidth can be increased, but the system becomes sensitive to matching imperfections and requires precise analog characteristic matching
Solution Approach 1:
The patent replaces the mechanical/analog multiplexer switching system with a digital processing system. Instead of using an analog multiplexer to combine sub-DAC outputs, the invention uses digital samples from multiple sub-DACs that are processed through digital filtering and summation. This substitution eliminates the sensitivity to analog matching imperfections while achieving the same bandwidth extension goal.
Solution Approach 2:
The patent introduces digital filtering as an intermediary process between the sub-DACs and the final output. The digital filter processes the digital samples to achieve the desired frequency response, replacing the need for precise analog matching in traditional multiplexer-based systems. This intermediary digital processing stage enables bandwidth extension without the reliability issues of analog matching.
2Speed
If high-frequency clocks are used to achieve high sampling rates, then signal bandwidth increases, but power consumption and circuit complexity increase
Solution Approach 1:
The patent divides the high-speed sampling task into multiple lower-speed sub-DACs operating in parallel. Instead of using a single DAC with a high-frequency clock, the system uses multiple sub-DACs with lower sampling rates that are combined through digital processing. This segmentation allows the use of slower, lower-power clocks while achieving the equivalent of high sampling rates through parallel processing.
Solution Approach 2:
The patent uses periodic interleaving of samples from multiple sub-DACs to achieve high effective sampling rates. By alternating between sub-DACs in a periodic manner and combining their outputs through digital filtering, the system achieves high bandwidth without requiring each individual sub-DAC to operate at high frequencies, thus reducing power consumption.
3Speed
If analog multiplexers are used to interleave samples from multiple sub-DACs, then bandwidth is extended, but device complexity increases
Solution Approach 1:
The patent replaces the analog multiplexer circuit with a digital processing architecture. Instead of using complex analog switching circuits to interleave samples, the invention uses digital sample buffering and processing. This substitution dramatically reduces circuit complexity while maintaining the bandwidth extension capability through digital filtering and summation of parallel sub-DAC outputs.
Data Source
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AI summary
A controlled switch having N inputs and a single output (N ≥ 2) is switchable between N states. In each state a respective one of the inputs is connected to the single output. There are N sources of sub-streams of analog samples, each sub-stream composed of pairs of adjacent analog samples. Each source is coupled to a respective one of the inputs. In operation, the controlled switch is controlled by a control signal to switch between the N states. While the controlled switch is in any one of the states, a data transition occurs between two adjacent analog samples in the sub-stream whose source is coupled to the input that is connected to the single output. The single output yields a high-bandwidth analog signal. Any pair of adjacent analog samples in any one of the sub-streams substantially determines a corresponding pair of adjacent analog samples in the high-bandwidth analog signal.